[coreboot] PATCH: IT8671F Select CLKIN

[Rudolf Marek]

Hi almost OK,

You deleted

it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, 0x00);

I would not trust the documentation if this is really a default value.

Please return it back.

Otherwise if this is fixed: Acked-by: Rudolf Marek <r.marek at assembler.cz>

Thanks,
Rudolf


Dne 9.5.2010 01:49, Anders Jenbo napsal(a):
> Ok done.
>
> -Anders
>
> søn, 09 05 2010 kl. 00:48 +0200, skrev Rudolf Marek:
>> -----BEGIN PGP SIGNED MESSAGE-----
>> Hash: SHA1
>>
>> Hi,
>>
>> Couple of issues to fix:
>>
>>
>>> Index: src/superio/ite/it8671f/it8671f_early_serial.c
>>> ===================================================================
>>> --- src/superio/ite/it8671f/it8671f_early_serial.c	(revision 5531)
>>> +++ src/superio/ite/it8671f/it8671f_early_serial.c	(working copy)
>>> @@ -53,12 +53,11 @@
>>>   	outb(value, SIO_DATA);
>>>   }
>>>
>>> -/* Enable the peripheral devices on the IT8671F Super I/O chip. */
>>> -static void it8671f_enable_serial(device_t dev, unsigned iobase)
>>> +static void it8671f_enter_conf(void)
>>>   {
>>>   	uint8_t i;
>>>
>>> -	/* (1) Enter the configuration state (MB PnP mode). */
>>> +	/*  Enter the configuration state (MB PnP mode). */
>>>
>>>   	/* Perform MB PnP setup to put the SIO chip at 0x3f0. */
>>>   	/* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
>>> @@ -74,20 +73,27 @@
>>>   		outb(init_values[i], SIO_BASE);
>>>   	}
>>>
>>> -	/* (2) Modify the data of configuration registers. */
>>> -
>>>   	/* Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2),
>>>              PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7). */
>>
>>
>> ^^^ this is not stuff for enable function. move it to enable serial where it was
>> please.
>>
>>>   	it8671f_sio_write(0x00, IT8671F_CONFIG_REG_LDE, 0x6f);
>>> +}
>>>
>>> +static void it8671f_exit_conf(void)
>>> +{
>>> +	/* Exit the configuration state (MB PnP mode). */
>>> +	it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02);
>>> +}
>>> +
>>> +void it8671f_48mhz_clkin(void)
>>> +{
>>> +	/* Select 48MHz CLKIN (24MHz default)*/
>>> +	it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, 0x40);
>>> +}
>>> +
>>> +/* Enable the peripheral devices on the IT8671F Super I/O chip. */
>>> +static void it8671f_enable_serial(device_t dev, unsigned iobase)
>>> +{
>>
>> you need to do call the it8671f_enter_conf(); here
>>>   	/* Enable serial port(s). */
>>>   	it8671f_sio_write(IT8671F_SP1,  0x30, 0x01); /* Serial port 1 */
>>>   	it8671f_sio_write(IT8671F_SP2,  0x30, 0x01); /* Serial port 2 */
>>> -
>>> -	/* Select 24MHz CLKIN (clear bit 6) and clear software suspend
>>> -	   mode (clear bit 0). */
>>> -	it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, 0x00);
>>> -
>>> -	/* (3) Exit the configuration state (MB PnP mode). */
>>> -	it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02);
>>
>> You need to call the it8671f_exit_conf(); here
>>
>>>   }
>>> Index: src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
>>> ===================================================================
>>> --- src/mainboard/soyo/sy-6ba-plus-iii/romstage.c	(revision 5531)
>>> +++ src/mainboard/soyo/sy-6ba-plus-iii/romstage.c	(working copy)
>>> @@ -53,7 +53,9 @@
>>>   	if (bist == 0)
>>>   		early_mtrr_init();
>>>
>>> +	it8671f_enter_conf();
>>>   	it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
>>> +	it8671f_exit_conf();
>> and not here
>>>   	uart_init();
>>>   	console_init();
>>>   	report_bist_failure(bist);
>>> Index: src/mainboard/gigabyte/ga-6bxc/romstage.c
>>> ===================================================================
>>> --- src/mainboard/gigabyte/ga-6bxc/romstage.c	(revision 5531)
>>> +++ src/mainboard/gigabyte/ga-6bxc/romstage.c	(working copy)
>>> @@ -53,7 +53,9 @@
>>>   	if (bist == 0)
>>>   		early_mtrr_init();
>>>
>>> +	it8671f_enter_conf();
>>>   	it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
>>> +	it8671f_exit_conf();
>>
>> same here
>>
>>>   	uart_init();
>>>   	console_init();
>>>   	report_bist_failure(bist);
>>>
>>>
>>
>> Thanks,
>> Rudolf
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>