[coreboot] Porting to RS780/SB700 board

Marc Jones marcj303 at gmail.com
Mon May 3 05:47:31 CEST 2010

On Sun, May 2, 2010 at 4:45 PM, Rudolf Marek <r.marek at assembler.cz> wrote:
> Hash: SHA1
> Rudolf Marek wrote:
>> I found that in k8 CAR set_var_mtrr is set as it the arguments would be an
>> adresses, but in fact they HAVE TO be in kilobytes.
> Hi again,
> I re-checked and it was OK, we do have an early function with same name which
> takes bytes parameters (mtrr-early.c). So this is not the case. I investigated
> MTRRs bit more.
> The RAM init on AMD does not use the varmtrr0 and varmtrr1 the reason is that it
> thinks the first is used for 0-RAMBASE second for ROM caching.
> I also changed the XIP MTRR setup to cache whole ROM with the MTRR. I think it
> is OK to do it this way...
> After the code goes to the post_cache_as_ram.c it sets up an mtrr for the
> coreboot_ram as 0-RAMTOP. Maybe we can go with a big mtrr 0-TOM and create UCs
> for VGA....
> Thanks,
> Rudolf

Hi Rudolf,

I was just looking at the same thing. I don't like the MTRR
manipulation that is happening in post_cache_as_ram.c. Doing 0-TOM is
a little tricky if the dimms are different sizes. It is easier to let
that get setup in the RAM stage. Getting the XIP setup correctly for
the lzma decompress seems to be an issue. I am not certain what is
happening and if we are crossing some boundaries that are causing
flushes. In addition to fixing the cache, Arne's patch to put the lzma
into memory may be the way to go.



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