[coreboot] RFC porting of SB7x00/RS78x boards

Rudolf Marek r.marek at assembler.cz
Sun Mar 21 21:19:30 CET 2010


Jason Wang napsal(a):
> hi Rudolf,
>   Since mass-porting to AMD 780 series mainboards is taken included in 
> GSoC 2010, the further work may be completed between this summer.

Hmm so I will wait again nearly next half of year? Not very nice. Therefore I 
would propose that we put in basically this patch in. And I would really 
appreciate that you do this board ASAP.

What about S3? Any ideas? I can try to work on this? Or?

Thanks,
Rudolf

> I would like to take all of your consideration as Reference for my 
> application.
> 
> best wishes.
> 
> Wang Qing Pei
> 
> On Sun, Mar 21, 2010 at 8:28 PM, Rudolf Marek <r.marek at assembler.cz 
> <mailto:r.marek at assembler.cz>> wrote:
> 
>     Hi all,
> 
>     I went bit more through the code, looks overall very good! Thanks AMD!
> 
>     Before we start the porting efforts here is the list of stuff needs
>     to be done.
> 
>     Is there anyone with spare time?
> 
>     1) move fadt.c into sb700 directory
> 
>     2) split ACPI dsl into smaller chunks, similar as we have for ICH7/945
> 
>     3) Check why resourcemap.c is needed. The only change from default
>     is change for
>     maximum bus number settings which is set to 8. Not sure if we really
>     need any
>     limit here?
> 
>     4) some DSDT methods are doing checks for Linux and do something
>     with AC97
>     codec, I think it does not work anyway because Linux tells it is
>     Windows to ACPI
>     :) Some DSDT values should be generated using ACPIgen namely HPET
>     and something
>     else I forgot already. The ITE code should go to separate file, the
>     _PTS method
>     is doing something to SMI, which we don't want because we dont have
>     any SMI trap
>     handler.
> 
>     5) The GFX reset stuff
> 
>     The Mahagony board has separate GFX reset GPIO because some PCIe 16x
>     are shared
>     with displayport.  I think this has to be checked for each board if
>     such GPIO
>     reset is needed.
> 
>     6) GPIO for IDE cable
>      This is also board dependent and must be find out.
> 
>     7) PCIe lanes setup. The RS780 has very flexible setup for PCIe
>     lanes, some for
>     them can be multiplexed for Display Port, some for HDMI etc... There is
>     something written in the DS of RS780 but it is hard to understand
>     that how it
>     suppose to work.
> 
>     #Define gpp_configuration,      A=0, B=1, C=2, D=3, E=4(default)
>     #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
>     #Define gfx_dev2_dev3, 0: a link will never be established on Dev2
>     or Dev3,
>     #                       1: the system allows a PCIE link to be
>     established on
>     Dev2 or Dev3.
>     #Define gfx_dual_slot, 0: single slot, 1: dual slot
>     #Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
>     #Define gfx_tmds, 0: didn't support TMDS, 1: support
>     #Define gfx_compliance, 0: didn't support compliance, 1: support
>     #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long
>     reconfiguration
>     #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not
>     supported), 6: x16
> 
>     Each board can setup this differently, gpp_configuration = 0 means
>     read it from
>     STRAP which is good because we dont have to set it up.
> 
> 
>     Is dual_slot - crossfire?
> 
>     Does TMDS here means DVI/HDMI?
> 
>     I try to get more ideas how this is supposed to work, maybe AMD
>     folks can also
>     help ;)
> 
>     Rudolf
> 
> 
>     -- 
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>     <mailto:coreboot at coreboot.org>
>     http://www.coreboot.org/mailman/listinfo/coreboot
> 
> 
> 
> 
> -- 
> Wang Qing Pei
> MSN:wangqingpei at hotmail.com <mailto:MSN%3Awangqingpei at hotmail.com>
> Gmail:wangqingpei at gmail.com <mailto:Gmail%3Awangqingpei at gmail.com>
> Phone:86+13426369984
> 




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