[coreboot] [PATCH] ASUS P2B-LS support, RAM detection for 440BX, add Slot 1 CPU, Microcode for Intel Tualatin CPUs

[Joseph Smith]

On Fri, 05 Mar 2010 15:24:25 +0100, Stefan Reinauer <stepan at coresystems.de>
wrote:
> On 3/5/10 3:15 PM, Joseph Smith wrote:
>>
>>
>> On Fri, 05 Mar 2010 13:04:27 +0000, Mark Marshall
<mark.marshall at csr.com>
>> wrote:
>>
>>> Joseph Smith wrote:
>>>
>>>> On 03/05/2010 03:03 AM, Mark Marshall wrote:
>>>>
>>>>> On 04/03/10 13:10, Joseph Smith wrote:
>>>>>
>>>>>> On 03/04/2010 07:38 AM, Joseph Smith wrote:
>>>>>>
>>>>>>> On 03/04/2010 07:30 AM, Uwe Hermann wrote:
>>>>>>>
>>>>>>>> On Thu, Mar 04, 2010 at 10:05:57AM +0000, Mark Marshall wrote:
>>>>>>>>
>>>>>>>>> On 03/03/10 04:19, Keith Hui wrote:
>>>>>>>>> The first problem is that this motherboard only has three DIMM
>>>>>>>>> slots. This means you have to set SDRAMC to something different;
>>>>>>>>> 0x0103 works for me.
>>>>>>>>>
>>>>>>>>>
>>>>>>>> Hm, seems to be determined by SDRAMPWR + MMCONFIG, and MMCONFIG
>>>>>>>> seems to
>>>>>>>> be a hardware-strap (so we can check it), but not sure about
>>>>>>>>
>>> SDRAMPWR.
>>>
>>>>>>>>
>>>>>>>>>
>>>>>> I think a simple SPD probe would work, if the correct value is
>>>>>>
>> returned
>>
>>>>>> you know you have memory in that slot, otherwise if 0xff is returned
>>>>>> then no memory is present. Do this probe for as many slots as the
440
>>>>>> supports. Then set your registers based on that.
>>>>>>
>>>>> The issue here is the number of DIMM slots on the motherboard, not
the
>>>>> number of sticks in the slots. Some 440BX boards have four slots,
> while
>>>>> others only have three.
>>>>>
>>>>> MM
>>>>>
>>>>>
>>>> That is fine. Then if 440bx datasheet says it supports 4 slots, then
>>>> that should be the standard.
>>>>
>>>>
>>> Please check this section of the 440BX data sheet.
>>>
>>>    3.3.24 SDRAMC—SDRAM Control Register (Device 0)
>>>
>>> We are interested in bit 4.
>>>
>>>   SDRAMPWR. The SDRAMPWR bit controls how the CKE signals are driven
>>>   for different DRAM configurations. For a 3 DIMM configuration,
>>>   SDRAMPWR should be set to ‘0’. For a 4 DIMM configuration,
>>>   SDRAMPWR should be set to ‘1’. In this case the 82443BX drives a
>>>   single CKE signal (GCKE). The combination of SDRAMPWR and MMCONFIG
>>>   (DRAMC register) determine the functioning of the CKE signals.
>>>   Refer to the DRAMC register (Section 3.3.15, “DRAMC—DRAM
>>>   Control Register (Device 0)” on page 3-19) for more details.
>>>
>>>   Note: When PCIRST# assertion occurs during POS/STR, these bits
>>>   are not reset to 0.
>>>
>>> As far as I can tell we cannot auto-detect this.  Some (many)
>>> 440BX boards only have three DIMM slots, and in these cases the
>>> clocks are routed differently to the boards with four DIMM slots.
>>>
>>>
>> That's easy... so you do something like this:
>>
>> slot4_detect = (spd_read_byte((DIMM_SPD_BASE + 3), SPD_MEMORY_TYPE);
>>
>> if (slot4_detect != 0xff) {
>>
>>      /* We have 4 slots */
>>      ----Set bit 4 in SDRAMPWR----
>>      #define DIMM_SOCKETS 4
>> } else {
>>
>>      /* We have 3 slots */
>>      ----Set bit 4 in SDRAMPWR----
>>      #define DIMM_SOCKETS 3
>> }
>>
>> Hope that helps.
>>
> 
> Will a mainboard with three modules but 4 slots work like this? Can
> someone try? If we can autodetect it, we should. If we can't I think
> encoding the number of slots in Kconfig is fine.
> 
I think so, from what I understand the clocks are routed in a daisy chain
so to speak. So if there is 4 physical slots and the system is only
configured for three it should work ok. Also this routine will be
determined at every start up so if you put a sdram module in the fourth
slot it will be re-configured for 4 slots.

Anyways the only way to know if this will work is to test it so can someone
please test?

Also, one could always use serialice on a 4 slot system with factory bios
to see how they deterime it....

One could try a dump with three DIMMS and then a dump with four DIMMS and
compare the results.


-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org