[coreboot] [commit] r5637 - in trunk/src: cpu/intel/socket_FC_PGA370 mainboard/intel/d810e2cb southbridge/intel/i82801bx
repository service
svn at coreboot.org
Tue Jun 22 01:25:06 CEST 2010
Author: linux_junkie
Date: Tue Jun 22 01:25:06 2010
New Revision: 5637
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5637
Log:
This patch adds support for the Intel D810E2CB (i810e/ICH2) desktop board. Hurray, this is the first i810 board running CAR.
Signed-off-by: Joseph Smith <joe at settoplinux.org>
Acked-by: Stefan Reinauer <stepan at coresystems.de>
Added:
trunk/src/mainboard/intel/d810e2cb/
trunk/src/mainboard/intel/d810e2cb/Kconfig
trunk/src/mainboard/intel/d810e2cb/chip.h
trunk/src/mainboard/intel/d810e2cb/devicetree.cb
trunk/src/mainboard/intel/d810e2cb/gpio.c
trunk/src/mainboard/intel/d810e2cb/irq_tables.c
trunk/src/mainboard/intel/d810e2cb/mainboard.c
trunk/src/mainboard/intel/d810e2cb/romstage.c
Modified:
trunk/src/cpu/intel/socket_FC_PGA370/Kconfig
trunk/src/southbridge/intel/i82801bx/i82801bx.h
trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c
Modified: trunk/src/cpu/intel/socket_FC_PGA370/Kconfig
==============================================================================
--- trunk/src/cpu/intel/socket_FC_PGA370/Kconfig Mon Jun 21 21:40:09 2010 (r5636)
+++ trunk/src/cpu/intel/socket_FC_PGA370/Kconfig Tue Jun 22 01:25:06 2010 (r5637)
@@ -23,3 +23,16 @@
select CPU_INTEL_MODEL_68X
select MMX
select SSE
+ select USE_PRINTK_IN_CAR
+ select USE_DCACHE_RAM
+ select TINY_BOOTBLOCK
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xffdf8000
+ depends on CPU_INTEL_SOCKET_FC_PGA370
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x8000
+ depends on CPU_INTEL_SOCKET_FC_PGA370
Added: trunk/src/mainboard/intel/d810e2cb/Kconfig
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ trunk/src/mainboard/intel/d810e2cb/Kconfig Tue Jun 22 01:25:06 2010 (r5637)
@@ -0,0 +1,52 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Joseph Smith <joe at settoplinux.org>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config BOARD_INTEL_D810E2CB
+ bool "D810E2CB"
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_FC_PGA370
+ select NORTHBRIDGE_INTEL_I82810
+ select SOUTHBRIDGE_INTEL_I82801BX
+ select SUPERIO_SMSC_SMSCSUPERIO
+ select HAVE_PIRQ_TABLE
+ select UDELAY_TSC
+ select BOARD_ROMSIZE_KB_512
+ select HAVE_MAINBOARD_RESOURCES
+ select GFXUMA
+
+config MAINBOARD_DIR
+ string
+ default intel/d810e2cb
+ depends on BOARD_INTEL_D810E2CB
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "D810E2CB"
+ depends on BOARD_INTEL_D810E2CB
+
+config HAVE_OPTION_TABLE
+ bool
+ default n
+ depends on BOARD_INTEL_D810E2CB
+
+config IRQ_SLOT_COUNT
+ int
+ default 7
+ depends on BOARD_INTEL_D810E2CB
+
Added: trunk/src/mainboard/intel/d810e2cb/chip.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ trunk/src/mainboard/intel/d810e2cb/chip.h Tue Jun 22 01:25:06 2010 (r5637)
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Joseph Smith <joe at settoplinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+struct mainboard_config {};
Added: trunk/src/mainboard/intel/d810e2cb/devicetree.cb
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ trunk/src/mainboard/intel/d810e2cb/devicetree.cb Tue Jun 22 01:25:06 2010 (r5637)
@@ -0,0 +1,82 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Joseph Smith <joe at settoplinux.org>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+chip northbridge/intel/i82810 # Northbridge
+ device lapic_cluster 0 on # APIC cluster
+ chip cpu/intel/socket_FC_PGA370 # CPU
+ device lapic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Graphics Memory Controller Hub (GMCH)
+ device pci 1.0 on end # Chipset Graphics Controller (CGC)
+ chip southbridge/intel/i82801bx # Southbridge
+ register "pirqa_routing" = "0x05"
+ register "pirqb_routing" = "0x06"
+ register "pirqc_routing" = "0x07"
+ register "pirqd_routing" = "0x09"
+ register "pirqe_routing" = "0x0a"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x0b"
+
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+
+ device pci 1e.0 on end # PCI bridge
+ device pci 1f.0 on # ISA bridge
+ chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47M102)
+ device pnp 4e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 4e.3 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 4
+ end
+ device pnp 4e.4 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 4e.5 off end # COM2
+ device pnp 4e.7 on # PS/2 keyboard / mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # PS/2 keyboard interrupt
+ irq 0x72 = 12 # PS/2 mouse interrupt
+ end
+ device pnp 4e.9 off end # Game port
+ device pnp 4e.a on # Runtime registers
+ io 0x60 = 0x800
+ end
+ device pnp 4e.b off end # MPU-401
+ end
+ end
+ device pci 1f.1 on end # IDE
+ device pci 1f.2 on end # USB
+ device pci 1f.3 on end # SMbus
+ device pci 1f.4 on end # USB
+ device pci 1f.5 on end # Audio controller
+ device pci 1f.6 off end # Modem controller
+ end
+ end
+end
Added: trunk/src/mainboard/intel/d810e2cb/gpio.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ trunk/src/mainboard/intel/d810e2cb/gpio.c Tue Jun 22 01:25:06 2010 (r5637)
@@ -0,0 +1,211 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Joseph Smith <joe at settoplinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define PME_DEV PNP_DEV(0x4e, 0x0a)
+#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */
+
+/* Early mainboard specific GPIO setup. */
+static void mb_gpio_init(void)
+{
+ device_t dev;
+ uint16_t port;
+
+ /* Southbridge GPIOs. */
+ /* Set the LPC device statically. */
+ dev = PCI_DEV(0x0, 0x1f, 0x0);
+
+ /* Set the value for GPIO base address register and enable GPIO. */
+ pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1));
+ pci_write_config8(dev, GPIO_CNTL, 0x10);
+
+ udelay(10);
+ outl(0x1a203180, GPIO_BASE_ADDR + 0x00); /* GPIO_USE_SEL */
+ outl(0x0000ffff, GPIO_BASE_ADDR + 0x04); /* GP_IO_SEL */
+ outl(0x13bf0000, GPIO_BASE_ADDR + 0x0c); /* GP_LVL */
+ outl(0x00040000, GPIO_BASE_ADDR + 0x18); /* GPO_BLINK */
+ outl(0x000039ff, GPIO_BASE_ADDR + 0x2c); /* GPI_INV */
+
+ /* Super I/O GPIOs. */
+ dev = PME_DEV;
+ port = dev >> 8;
+
+ /* Enter the configuration state. */
+ outb(0x55, port);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
+ pnp_set_enable(dev, 1);
+
+ /* GP10 - J1B1 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x23);
+
+ /* GP11 - J1B2 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x24);
+
+ /* GP12 - J2B1 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x25);
+
+ /* GP13 - J2B2 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x26);
+
+ /* GP14 - J1X */
+ outl(0x01, PME_IO_BASE_ADDR + 0x27);
+
+ /* GP15 - J1Y */
+ outl(0x01, PME_IO_BASE_ADDR + 0x28);
+
+ /* GP16 - J2X */
+ outl(0x01, PME_IO_BASE_ADDR + 0x29);
+
+ /* GP17 - J2Y */
+ outl(0x01, PME_IO_BASE_ADDR + 0x2a);
+
+ /* GP20 - 8042 P17 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x2b);
+
+ /* GP21 - 8042 P16 */
+ outl(0x00, PME_IO_BASE_ADDR + 0x2c);
+
+ /* GP22 - 8042 P12 */
+ outl(0x00, PME_IO_BASE_ADDR + 0x2d);
+
+ /* GP24 */
+ outl(0x00, PME_IO_BASE_ADDR + 0x2f);
+
+ /* GP25 - MIDI_IN */
+ outl(0x01, PME_IO_BASE_ADDR + 0x30);
+
+ /* GP26 - MIDI_OUT */
+ outl(0x01, PME_IO_BASE_ADDR + 0x31);
+
+ /* GP27 - nIO_SMI */
+ outl(0x04, PME_IO_BASE_ADDR + 0x32);
+
+ /* GP30 - FAN_TACH2 */
+ outl(0x05, PME_IO_BASE_ADDR + 0x33);
+
+ /* GP31 - FAN_TACH1 */
+ outl(0x05, PME_IO_BASE_ADDR + 0x34);
+
+ /* GP32 - FAN2 */
+ outl(0x04, PME_IO_BASE_ADDR + 0x35);
+
+ /* GP33 - FAN1 */
+ outl(0x04, PME_IO_BASE_ADDR + 0x36);
+
+ /* GP34 - IRRX2 */
+ outl(0x05, PME_IO_BASE_ADDR + 0x37);
+
+ /* GP35 - IRTX2 */
+ outl(0x04, PME_IO_BASE_ADDR + 0x38);
+
+ /* GP36 - nKBDRST */
+ outl(0x84, PME_IO_BASE_ADDR + 0x39);
+
+ /* GP37 - A20M */
+ outl(0x84, PME_IO_BASE_ADDR + 0x3a);
+
+ /* GP40 - DRVDEN0 */
+ outl(0x04, PME_IO_BASE_ADDR + 0x3b);
+
+ /* GP41 - DRVDEN1 */
+ outl(0x04, PME_IO_BASE_ADDR + 0x3c);
+
+ /* GP42 - nIO_PME */
+ outl(0x84, PME_IO_BASE_ADDR + 0x3d);
+
+ /* GP43 */
+ outl(0x00, PME_IO_BASE_ADDR + 0x3e);
+
+ /* GP50 - nIR2 */
+ outl(0x05, PME_IO_BASE_ADDR + 0x3f);
+
+ /* GP51 - nDCD2 */
+ outl(0x05, PME_IO_BASE_ADDR + 0x40);
+
+ /* GP52 - RXD2 */
+ outl(0x05, PME_IO_BASE_ADDR + 0x41);
+
+ /* GP53 - TXD2 */
+ outl(0x04, PME_IO_BASE_ADDR + 0x42);
+
+ /* GP54 - nDSR2 */
+ outl(0x05, PME_IO_BASE_ADDR + 0x43);
+
+ /* GP55 - nRTS2 */
+ outl(0x04, PME_IO_BASE_ADDR + 0x44);
+
+ /* GP56 - nCTS2 */
+ outl(0x05, PME_IO_BASE_ADDR + 0x45);
+
+ /* GP57 - nDTR2 */
+ outl(0x04, PME_IO_BASE_ADDR + 0x46);
+
+ /* GP60 - LED1 */
+ outl(0x84, PME_IO_BASE_ADDR + 0x47);
+
+ /* GP61 - LED2 */
+ outl(0x84, PME_IO_BASE_ADDR + 0x48);
+
+ /* GP1 */
+ outl(0x00, PME_IO_BASE_ADDR + 0x4b);
+
+ /* GP2 */
+ outl(0x14, PME_IO_BASE_ADDR + 0x4c);
+
+ /* GP3 */
+ outl(0xda, PME_IO_BASE_ADDR + 0x4d);
+
+ /* GP4 */
+ outl(0x08, PME_IO_BASE_ADDR + 0x4e);
+
+ /* GP5 */
+ outl(0x00, PME_IO_BASE_ADDR + 0x4f);
+
+ /* GP6 */
+ outl(0x00, PME_IO_BASE_ADDR + 0x50);
+
+ /* FAN1 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x56);
+
+ /* FAN2 */
+ outl(0x01, PME_IO_BASE_ADDR + 0x57);
+
+ /* Fan Control */
+ outl(0xf0, PME_IO_BASE_ADDR + 0x58);
+
+ /* Fan1 Preload */
+ outl(0x00, PME_IO_BASE_ADDR + 0x5b);
+
+ /* Fan2 Preload */
+ outl(0x00, PME_IO_BASE_ADDR + 0x5c);
+
+ /* LED1 */
+ outl(0x03, PME_IO_BASE_ADDR + 0x5d);
+
+ /* LED2 */
+ outl(0x03, PME_IO_BASE_ADDR + 0x5e);
+
+ /* Keyboard Scan Code */
+ outl(0x00, PME_IO_BASE_ADDR + 0x5f);
+
+ /* Exit the configuration state. */
+ outb(0xaa, port);
+}
Added: trunk/src/mainboard/intel/d810e2cb/irq_tables.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ trunk/src/mainboard/intel/d810e2cb/irq_tables.c Tue Jun 22 01:25:06 2010 (r5637)
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Joseph Smith <joe at settoplinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus (7)*/
+ 0x00, /* Interrupt router bus */
+ (0x1f << 3) | 0x0, /* Interrupt router dev */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x8086, /* Vendor */
+ 0x2440, /* Device */
+ 0, /* Miniport */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0xd9, /* Checksum (has to be set to some value that
+ * would give 0 after the sum of all bytes
+ * for this structure (including checksum).
+ */
+ {
+ /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00, (0x00 << 3) | 0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdeb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x1e << 3) | 0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x1f << 3) | 0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x6b, 0xdef8}, {0x63, 0xdef8}}, 0x0, 0x0},
+ {0x01, (0x01 << 3) | 0x0, {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}}, 0x1, 0x0},
+ {0x01, (0x02 << 3) | 0x0, {{0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}}, 0x2, 0x0},
+ {0x01, (0x08 << 3) | 0x0, {{0x68, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr);
+}
Added: trunk/src/mainboard/intel/d810e2cb/mainboard.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ trunk/src/mainboard/intel/d810e2cb/mainboard.c Tue Jun 22 01:25:06 2010 (r5637)
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Joseph Smith <joe at settoplinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <boot/tables.h>
+#include "chip.h"
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return add_northbridge_resources(mem);
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Intel D810E2CB Mainboard")
+};
Added: trunk/src/mainboard/intel/d810e2cb/romstage.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ trunk/src/mainboard/intel/d810e2cb/romstage.c Tue Jun 22 01:25:06 2010 (r5637)
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Joseph Smith <joe at settoplinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include <console/console.h>
+#include "lib/ramtest.c"
+#include "southbridge/intel/i82801bx/i82801bx.h"
+#include "southbridge/intel/i82801bx/i82801bx_early_smbus.c"
+#include "northbridge/intel/i82810/raminit.h"
+#include "lib/debug.c"
+#include "pc80/udelay_io.c"
+#include "lib/delay.c"
+#include "cpu/x86/bist.h"
+#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+#include "gpio.c"
+
+#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
+
+static inline int spd_read_byte(unsigned int device, unsigned int address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include "northbridge/intel/i82810/raminit.c"
+/* #include "northbridge/intel/i82810/debug.c" */
+
+void main(unsigned long bist)
+{
+ /* Set southbridge and superio gpios */
+ mb_gpio_init();
+
+ smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ uart_init();
+ console_init();
+
+ report_bist_failure(bist);
+ enable_smbus();
+ /* dump_spd_registers(); */
+ sdram_set_registers();
+ sdram_set_spd_registers();
+ sdram_enable();
+ /* ram_check(0, 640 * 1024); */
+}
+
Modified: trunk/src/southbridge/intel/i82801bx/i82801bx.h
==============================================================================
--- trunk/src/southbridge/intel/i82801bx/i82801bx.h Mon Jun 21 21:40:09 2010 (r5636)
+++ trunk/src/southbridge/intel/i82801bx/i82801bx.h Tue Jun 22 01:25:06 2010 (r5637)
@@ -37,10 +37,8 @@
#define PMBASE_ADDR 0x0400 /* ACPI Base Address Register */
#define ACPI_CNTL 0x44
#define BIOS_CNTL 0x4E
-#define GPIO_BASE_ICH0_5 0x58 /* LPC GPIO Base Addr. Reg. (ICH0-ICH5) */
-#define GPIO_BASE_ICH6_9 0x48 /* LPC GPIO Base Address Register (ICH6-ICH9) */
-#define GPIO_CNTL_ICH0_5 0x5C /* LPC GPIO Control Register (ICH0-ICH5) */
-#define GPIO_CNTL_ICH6_9 0x4C /* LPC GPIO Control Register (ICH6-ICH9) */
+#define GPIO_BASE 0x58 /* LPC GPIO Base Address Register */
+#define GPIO_CNTL 0x5C /* LPC GPIO Control Register */
#define PIRQA_ROUT 0x60
#define PIRQB_ROUT 0x61
@@ -69,6 +67,8 @@
#define MTT 0x70
#define PCI_MAST_STS 0x82
+#define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */
+
#define TCOBASE 0x60 /* TCO Base Address Register */
#define TCO1_CNT 0x08 /* TCO1 Control Register */
Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c
==============================================================================
--- trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c Mon Jun 21 21:40:09 2010 (r5636)
+++ trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c Tue Jun 22 01:25:06 2010 (r5637)
@@ -32,8 +32,6 @@
#include <arch/io.h>
#include "i82801bx.h"
-#define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */
-
#define NMI_OFF 0
typedef struct southbridge_intel_i82801bx_config config_t;
@@ -206,18 +204,11 @@
}
}
-static void gpio_init(device_t dev, uint16_t ich_model)
+static void gpio_init(device_t dev)
{
- /* Set the value for GPIO base address register and enable GPIO.
- * Note: ICH-ICH5 registers differ from ICH6-ICH9.
- */
- if (ich_model <= 0x24D0) {
- pci_write_config32(dev, GPIO_BASE_ICH0_5, (GPIO_BASE_ADDR | 1));
- pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
- } else if (ich_model >= 0x2640) {
- pci_write_config32(dev, GPIO_BASE_ICH6_9, (GPIO_BASE_ADDR | 1));
- pci_write_config8(dev, GPIO_CNTL_ICH6_9, 0x10);
- }
+ /* Set the value for GPIO base address register and enable GPIO. */
+ pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1));
+ pci_write_config8(dev, GPIO_CNTL, 0x10);
}
void i82801bx_rtc_init(struct device *dev)
@@ -291,7 +282,7 @@
i82801bx_power_options(dev);
/* Set the state of the GPIO lines. */
- gpio_init(dev, ich_model);
+ gpio_init(dev);
/* Initialize the real time clock. */
i82801bx_rtc_init(dev);
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