[coreboot] coreboot Digest, Vol 64, Issue 23

Keith Hui buurin at gmail.com
Mon Jun 7 18:17:17 CEST 2010

Yes, I have it. Thanks to all who responded. Looks like there is only
two versions of the datasheet out, but I have a intact version now.

It may not be enough to help me write from scratch, but will help me
understand the factory BIOS's ways. Now, I have a 630ET that also have
Tualatin support, and my board's bootblock is already conditionally
setting some "reserved" bits when a Tualatin chip is installed.
There's also some flipping of GPIO4 and GPIO7 (thanks to the
datasheets now I know) for unknown purposes. There's also nothing
about RAM sizing algorithm. There is also the same SRAM chip as P3B-F
has which flashrom doesn't work with. Even better, there will be
board-specific enable needed when it comes time to do flashrom. Oh
yeah, the MAC address for the built in LAN is in the flash.

Good news is, IDE controller for many SIS chipsets (630 included) are
all identified as "5513" meaning I should be able to bring in
something from other SiS chipset(s) already in the tree.

Also, how should the code be organized? 630 series is a single chip.
The main other separate chips are IT8705 for super I/O, and CMI8738
for audio that I don't need to worry about for now. Question is - All
in src/northbridge?

But before I go any further, I have to reinstall my main
HTPC-cum-broadband-router that have been having problems for months.

As for my board, after I soldered on a PLCC socket, it has to return
to active service as the backup router while I reinstall the other
machine (above).

And there is also the lingering problem of the SCSI chip on my P2B-LS
board still not working properly, and there's also ACPI support/SMI
handler for same. So it will be a while.


> From: Darmawan Salihun <darmawan.salihun at gmail.com>
> Date: Mon, 7 Jun 2010 20:00:08 +0700
> Subject: Re: [coreboot] SIS630ET coreboot challenge
> To: Tiago Marques <tiagomnm at gmail.com>
> I've sent a datasheet in my posession to Keith. Haven't heard back
> from him yet. Hopefully he can make use of it :-)
> On 6/6/10, Tiago Marques <tiagomnm at gmail.com> wrote:
>> Me? I wasn't after that.
>> Best regards
>> On Sat, Jun 5, 2010 at 9:32 AM, Stefan Reinauer <
>> stefan.reinauer at coresystems.de> wrote:
>>> On 6/5/10 5:15 AM, Tiago Marques wrote:
>>> > See the attachment, doesn't look like something from a company that's
>>> > alive and kicking. I know them since the SiS 730.
>>> > Last time I heard they had some design win for a Core 2 chipset that I
>>> > haven't seen in any product and started selling SiS branded SO-DIMMS :|
>>> >
>>> So you did contact them for data sheets?
>>> --
>>> coreboot mailing list: coreboot at coreboot.org
>>> http://www.coreboot.org/mailman/listinfo/coreboot

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