[coreboot] What is the rule of the SPD address assignment if there are more that 8 dimm slots?

[ron minnich]

2010/7/31 Zheng Bao <fishbaoz at hotmail.com>:
> The board tht I am working on has 2 process. Each of them has 6 DIMM slots.
> If you
> plug 1 dimm into each slot, the SPD address will be,
>   Channel  PCB
>   ----------------
> P0:
>   DIMMA0   50h
>   DIMMA1   51h
>   DIMMA2   52h
>   DIMMB0   53h
>   DIMMB1   54h
>   DIMMB2   55h
> P1:
>   DIMMA0   50h
>   DIMMA1   51h
>   DIMMA2   52h
>   DIMMB0   53h
>   DIMMB1   54h
>   DIMMB2   55h
> If you plug 1 dimm in P0DIMMA0 and the other in P1DIMA0, the SPD address
> will be 50h and 55h.
> So I am confused. If we got an active spd 0x50 on the SMBUS, what will it
> be?

Are you sure the wiring is correct? Can you plug the DIMM into
P1DIMMB2 and see what SPD address it has? This could be a simple case
of an error in the wiring.

What does the standard say about SPD addressing of DIMMs? It's more
than a 3 bit address and it seems we must have more addresses in the
definition.

ron