[coreboot] [PATCH][inteltool] Support for Atom D/N series and Q963/965

[Paul Menzel]

Am Donnerstag, den 29.07.2010, 03:08 -0400 schrieb Corey Osgood:
> Add support for the Intel Atom D400/500- and N400-series integrated 
> northbridge. Also add support for the very similar Q963/965
> northbridge.
> Tested: 
>   D510: confirmed working, with MCHBAR enable code
>   Q965: writes to bit 0 to enable MCHBAR access are ignored, all other
> functions work
> 
> Untested:
>   D410/D525/N400: should be the same northbridge

Maybe add a link to the datasheets to the commit message.

> Signed-off-by: Corey Osgood <corey.osgood at gmail.com>

Acked-by: Paul Menzel <paulepanter at users.sourceforge.net>

If you want to you could add full stops add the end of sentences.

[…]

> Index: memory.c
> ===================================================================
> --- memory.c    (revision 5670)
> +++ memory.c    (working copy)
> @@ -47,6 +47,32 @@
>                 mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
>                 mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
>                 break;
> +       case PCI_DEVICE_ID_INTEL_Q965:
> +       case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
> +       case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
> +               mchbar_phys = pci_read_long(nb, 0x48);
> +
> +               /* Test if bit 0 of the MCHBAR reg is 1 to enable memory reads.
> +                * If it isn't, try to set it. This may fail, because there is 
> +                * some bit that locks that bit, and isn't in the public 
> +                * datasheets.
> +                */
> +
> +               if(!(mchbar_phys & 1))
> +               {
> +                       printf("Access to the MCHBAR is currently disabled, "\
> +                                               "attempting to enable\n");

Full stop at the end of the sentence.

> +                       mchbar_phys |= 0x1;
> +                       pci_write_long(nb, 0x48, mchbar_phys);
> +                       mchbar_phys = pci_read_long(nb, 0x48);
> +                       if(pci_read_long(nb, 0x48) & 1)
> +                               printf("Enabled successfully\n");

Dito.

> +                       else
> +                               printf("Enable FAILED!\n");
> +               }
> +               mchbar_phys &= 0xfffffffe;
> +               mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
> +               break;
>         case PCI_DEVICE_ID_INTEL_82443LX:
>         case PCI_DEVICE_ID_INTEL_82443BX:
>         case PCI_DEVICE_ID_INTEL_82810:

[…]
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