[coreboot] GIGABYTE GA785GMT-UD2H coreboot porting problems
Qing Pei Wang
wangqingpei at gmail.com
Mon Jul 19 12:54:43 CEST 2010
hi,
i am trying to port coreboot to 785/710 mainboard which is gigabyte
ga785gmt-ud2h.
the problem now is it reboots while decompress cbfs by executing "memcpy".
i would like to doubt that ddr3 is not configured correctly.
the log is attached.
any suggestion is welcome.
thanks
--
Wang Qing Pei
Phone: 86+13426369984
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coreboot-4.0-r759M Mon Jul 19 16:15:56 CST 2010 starting...
BSP Family_Model: 00100f63
*sysinfo range: [000cc000,000cf360]
bsp_apicid = 00
cpu_init_detectedx = 00000000
microcode: equivalent rev id = 0x1043, current patch id = 0x00000000
microcode: patch id to apply = 0x010000b6
microcode: updated to patch id = 0x010000b6 success
cpuSetAMDMSR done
Enter amd_ht_init()
AMD_CB_EventNotify()
event class: 05
event: 2006
data: 04 00 00 00
Exit amd_ht_init()
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
F3x80: e600a681
F3x84: a0e641e6
F3xD4: c8810f25
F3xD8: 03000714
F3xDC: 0000522c
core0 started:
start_other_cores()
init node: 00 cores: 00
started ap apicid:
rs780_early_setup()
get_cpu_rev EAX=0x100f63.
CPU Rev is K8_10.
fam10_optimization()
rs780_por_init
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-18-0
sb700_pmio_por_init()
Begin FIDVID MSR 0xc0010071 0x28a40112 0x44025840
FIDVID on BSP, APIC_id: 00
BSP fid = 10500
common_fid = 10500
FID Change Node:00, F3xD4: c8810f25
End FIDVIDMSR 0xc0010071 0x28a40112 0x44025840
rs780_htinit cpu_ht_freq=a.
rs780_htinit: HT3 mode
...WARM RESET...
coreboot-4.0-r759M Mon Jul 19 16:15:56 CST 2010 starting...
BSP Family_Model: 00100f63
*sysinfo range: [000cc000,000cf360]
bsp_apicid = 00
cpu_init_detectedx = 00000000
microcode: equivalent rev id = 0x1043, current patch id = 0x00000000
microcode: patch id to apply = 0x010000b6
microcode: updated to patch id = 0x010000b6 success
cpuSetAMDMSR done
Enter amd_ht_init()
AMD_CB_EventNotify()
event class: 05
event: 2006
data: 04 00 00 00
Exit amd_ht_init()
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
F3x80: e600a681
F3x84: a0e641e6
F3xD4: c8810f25
F3xD8: 03000714
F3xDC: 0000522c
core0 started:
start_other_cores()
init node: 00 cores: 00
started ap apicid:
rs780_early_setup()
get_cpu_rev EAX=0x100f63.
CPU Rev is K8_10.
fam10_optimization()
rs780_por_init
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-18-0
sb700_pmio_por_init()
Begin FIDVID MSR 0xc0010071 0x28a40112 0x44025840
End FIDVIDMSR 0xc0010071 0x28a40112 0x44004402
rs780_htinit cpu_ht_freq=a.
rs780_htinit: HT3 mode
fill_mem_ctrl()
raminit_amdmct()
raminit_amdmct begin:
DIMMPresence: DIMMValid=2
DIMMPresence: DIMMPresent=2
DIMMPresence: RegDIMMPresent=0
DIMMPresence: DimmECCPresent=0
DIMMPresence: DimmPARPresent=0
DIMMPresence: Dimmx4Present=0
DIMMPresence: Dimmx8Present=2
DIMMPresence: Dimmx16Present=0
DIMMPresence: DimmPlPresent=0
DIMMPresence: DimmDRPresent=0
DIMMPresence: DimmQRPresent=0
DIMMPresence: DATAload[0]=0
DIMMPresence: MAload[0]=0
DIMMPresence: MAdimms[0]=0
DIMMPresence: DATAload[1]=1
DIMMPresence: MAload[1]=8
DIMMPresence: MAdimms[1]=1
DIMMPresence: Status 1000
DIMMPresence: ErrStatus 0
DIMMPresence: ErrCode 0
DIMMPresence: Done
DCTInit_D: mct_DIMMPresence Done
SPDCalcWidth: Status 1000
SPDCalcWidth: ErrStatus 0
SPDCalcWidth: ErrCode 0
SPDCalcWidth: Done
DCTInit_D: mct_SPDCalcWidth Done
SPDGetTCL_D: DIMMCASL 4
SPDGetTCL_D: DIMMAutoSpeed 4
SPDGetTCL_D: Status 1000
SPDGetTCL_D: ErrStatus 0
SPDGetTCL_D: ErrCode 0
SPDGetTCL_D: Done
AutoCycTiming: Status 1000
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 2
AutoCycTiming: Done
DCTInit_D: mct_DIMMPresence Done
SPDCalcWidth: Status 1000
SPDCalcWidth: ErrStatus 0
SPDCalcWidth: ErrCode 0
SPDCalcWidth: Done
DCTInit_D: mct_SPDCalcWidth Done
AutoCycTiming: Status 1000
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 0
AutoCycTiming: Done
DCTInit_D: AutoCycTiming_D Done
SPDSetBanks: CSPresent 1
SPDSetBanks: Status 1000
SPDSetBanks: ErrStatus 0
SPDSetBanks: ErrCode 0
SPDSetBanks: Done
AfterStitch pDCTstat->NodeSysBase = 0
mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffff
StitchMemory: Status 1000
StitchMemory: ErrStatus 0
StitchMemory: ErrCode 0
StitchMemory: Done
InterleaveBanks_D: Status 1000
InterleaveBanks_D: ErrStatus 80
InterleaveBanks_D: ErrCode 0
InterleaveBanks_D: Done
AutoConfig_D: DramControl: 2a06
AutoConfig_D: DramTimingLo: a0092
AutoConfig_D: DramConfigMisc: 0
AutoConfig_D: DramConfigMisc2: 0
AutoConfig_D: DramConfigLo: 8010000
AutoConfig_D: DramConfigHi: f48000b
AutoConfig: Status 1000
AutoConfig: ErrStatus 80
AutoConfig: ErrCode 0
AutoConfig: Done
DCTInit_D: AutoConfig_D Done
DCTInit_D: PlatformSpec_D Done
DCTInit_D: StartupDCT_D
mctAutoInitMCT_D: SyncDCTsReady_D
mctAutoInitMCT_D: HTMemMapInit_D
Node: 00 base: 00 limit: 3fffff BottomIO: e00000
Node: 00 base: 03 limit: 3fffff
Node: 01 base: 00 limit: 00
Node: 02 base: 00 limit: 00
Node: 03 base: 00 limit: 00
Node: 04 base: 00 limit: 00
Node: 05 base: 00 limit: 00
Node: 06 base: 00 limit: 00
Node: 07 base: 00 limit: 00
mctAutoInitMCT_D: CPUMemTyping_D
CPUMemTyping: Cache32bTOP:400000
CPUMemTyping: Bottom32bIO:400000
CPUMemTyping: Bottom40bIO:0
mctAutoInitMCT_D: DQSTiming_D
TrainRcvrEn: Status 1000
TrainRcvrEn: ErrStatus 80
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done
TrainDQSRdWrPos: Status 1000
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 80
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
TrainDQSRdWrPos: Status 1000
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 80
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
TrainDQSRdWrPos: Status 1000
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 80
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
TrainDQSRdWrPos: Status 1000
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 80
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
mctAutoInitMCT_D: UMAMemTyping_D
mctAutoInitMCT
coreboot-4.0-r759M Mon Jul 19 16:15:56 CST 2010 starting...
BSP Family_Model: 00100f63
*sysinfo range: [000cc000,000cf360]
bsp_apicid = 00
cpu_init_detectedx = 00000000
microcode: equivalent rev id = 0x1043, current patch id = 0x00000000
microcode: patch id to apply = 0x010000b6
microcode: updated to patch id = 0x010000b6 success
cpuSetAMDMSR done
Enter amd_ht_init()
AMD_CB_EventNotify()
event class: 05
event: 2006
data: 04 00 00 00
Exit amd_ht_init()
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
F3x80: e600a681
F3x84: a0e641e6
F3xD4: c8810f25
F3xD8: 03000714
F3xDC: 0000522c
core0 started:
start_other_cores()
init node: 00 cores: 00
started ap apicid:
rs780_early_setup()
get_cpu_rev EAX=0x100f63.
CPU Rev is K8_10.
fam10_optimization()
rs780_por_init
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-18-0
sb700_pmio_por_init()
Begin FIDVID MSR 0xc0010071 0x28a40112 0x44025840
FIDVID on BSP, APIC_id: 00
BSP fid = 10500
common_fid = 10500
FID Change Node:00, F3xD4: c8810f25
End FIDVIDMSR 0xc0010071 0x28a40112 0x44025840
rs780_htinit cpu_ht_freq=a.
rs780_htinit: HT3 mode
...WARM RESET...
coreboot-4.0-r759M Mon Jul 19 16:15:56 CST 2010 starting...
BSP Family_Model: 00100f63
*sysinfo range: [000cc000,000cf360]
bsp_apicid = 00
cpu_init_detectedx = 00000000
microcode: equivalent rev id = 0x1043, current patch id = 0x00000000
microcode: patch id to apply = 0x010000b6
microcode: updated to patch id = 0x010000b6 success
cpuSetAMDMSR done
Enter amd_ht_init()
AMD_CB_EventNotify()
event class: 05
event: 2006
data: 04 00 00 00
Exit amd_ht_init()
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
F3x80: e600a681
F3x84: a0e641e6
F3xD4: c8810f25
F3xD8: 03000714
F3xDC: 0000522c
core0 started:
start_other_cores()
init node: 00 cores: 00
started ap apicid:
rs780_early_setup()
get_cpu_rev EAX=0x100f63.
CPU Rev is K8_10.
fam10_optimization()
rs780_por_init
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-18-0
sb700_pmio_por_init()
Begin FIDVID MSR 0xc0010071 0x28a40112 0x44025840
End FIDVIDMSR 0xc0010071 0x28a40112 0x44004402
rs780_htinit cpu_ht_freq=a.
rs780_htinit: HT3 mode
fill_mem_ctrl()
raminit_amdmct()
raminit_amdmct begin:
DIMMPresence: DIMMValid=2
DIMMPresence: DIMMPresent=2
DIMMPresence: RegDIMMPresent=0
DIMMPresence: DimmECCPresent=0
DIMMPresence: DimmPARPresent=0
DIMMPresence: Dimmx4Present=0
DIMMPresence: Dimmx8Present=2
DIMMPresence: Dimmx16Present=0
DIMMPresence: DimmPlPresent=0
DIMMPresence: DimmDRPresent=0
DIMMPresence: DimmQRPresent=0
DIMMPresence: DATAload[0]=0
DIMMPresence: MAload[0]=0
DIMMPresence: MAdimms[0]=0
DIMMPresence: DATAload[1]=1
DIMMPresence: MAload[1]=8
DIMMPresence: MAdimms[1]=1
DIMMPresence: Status 1000
DIMMPresence: ErrStatus 0
DIMMPresence: ErrCode 0
DIMMPresence: Done
DCTInit_D: mct_DIMMPresence Done
SPDCalcWidth: Status 1000
SPDCalcWidth: ErrStatus 0
SPDCalcWidth: ErrCode 0
SPDCalcWidth: Done
DCTInit_D: mct_SPDCalcWidth Done
SPDGetTCL_D: DIMMCASL 4
SPDGetTCL_D: DIMMAutoSpeed 4
SPDGetTCL_D: Status 1000
SPDGetTCL_D: ErrStatus 0
SPDGetTCL_D: ErrCode 0
SPDGetTCL_D: Done
AutoCycTiming: Status 1000
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 2
AutoCycTiming: Done
DCTInit_D: mct_DIMMPresence Done
SPDCalcWidth: Status 1000
SPDCalcWidth: ErrStatus 0
SPDCalcWidth: ErrCode 0
SPDCalcWidth: Done
DCTInit_D: mct_SPDCalcWidth Done
AutoCycTiming: Status 1000
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 0
AutoCycTiming: Done
DCTInit_D: AutoCycTiming_D Done
SPDSetBanks: CSPresent 1
SPDSetBanks: Status 1000
SPDSetBanks: ErrStatus 0
SPDSetBanks: ErrCode 0
SPDSetBanks: Done
AfterStitch pDCTstat->NodeSysBase = 0
mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffff
StitchMemory: Status 1000
StitchMemory: ErrStatus 0
StitchMemory: ErrCode 0
StitchMemory: Done
InterleaveBanks_D: Status 1000
InterleaveBanks_D: ErrStatus 80
InterleaveBanks_D: ErrCode 0
InterleaveBanks_D: Done
AutoConfig_D: DramControl: 2a06
AutoConfig_D: DramTimingLo: a0092
AutoConfig_D: DramConfigMisc: 0
AutoConfig_D: DramConfigMisc2: 0
AutoConfig_D: DramConfigLo: 8010000
AutoConfig_D: DramConfigHi: f48000b
AutoConfig: Status 1000
AutoConfig: ErrStatus 80
AutoConfig: ErrCode 0
AutoConfig: Done
DCTInit_D: AutoConfig_D Done
DCTInit_D: PlatformSpec_D Done
DCTInit_D: StartupDCT_D
mctAutoInitMCT_D: SyncDCTsReady_D
mctAutoInitMCT_D: HTMemMapInit_D
Node: 00 base: 00 limit: 3fffff BottomIO: e00000
Node: 00 base: 03 limit: 3fffff
Node: 01 base: 00 limit: 00
Node: 02 base: 00 limit: 00
Node: 03 base: 00 limit: 00
Node: 04 base: 00 limit: 00
Node: 05 base: 00 limit: 00
Node: 06 base: 00 limit: 00
Node: 07 base: 00 limit: 00
mctAutoInitMCT_D: CPUMemTyping_D
CPUMemTyping: Cache32bTOP:400000
CPUMemTyping: Bottom32bIO:400000
CPUMemTyping: Bottom40bIO:0
mctAutoInitMCT_D: DQSTiming_D
TrainRcvrEn: Status 1000
TrainRcvrEn: ErrStatus 80
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done
TrainDQSRdWrPos: Status 1000
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 80
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
TrainDQSRdWrPos: Status 1000
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 80
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
TrainDQSRdWrPos: Status 1000
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 80
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
TrainDQSRdWrPos: Status 1000
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 80
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
mctAutoInitMCT_D: UMAMemTyping_D
mctAutoInitMCT_D: :OtherTiming
InterleaveNodes_D: Status 1000
InterleaveNodes_D: ErrStatus 80
InterleaveNodes_D: ErrCode 0
InterleaveNodes_D: Done
InterleaveChannels_D: Node 0
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 80
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 1
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 2
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 3
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 4
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 5
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 6
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 7
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Done
mctAutoInitMCT_D: ECCInit_D
All Done
raminit_amdmct end:
*** Yes, the copy/decompress is taking a while, FIXME!
v_esp=000cbf48
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now
Clearing initial memory region: Done
Loading stage image.
Check CBFS header at fffffd2e
magic is 4f524243
Found CBFS header at fffffd2e
Check fallback/romstage
CBFS: follow chain: fff00000 + 38 + 17191 + align -> fff17200
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x200000 (1245184 bytes), entry @ 0x200000
CBFS: got here src=fff17254,dest=200000,len=30000
coreboot-4.0-r759M Mon Jul 19 16:15:56 CST 2010 starting...
BSP Family_Model: 00100f63
*sysinfo range: [000cc000,000cf360]
bsp_apicid = 00
cpu_init_detectedx = 00000000
microcode: equivalent rev id = 0x1043, current patch id = 0x00000000
microcode: patch id to apply = 0x010000b6
microcode: updated to patch id = 0x010000b6 success
cpuSetAMDMSR done
Enter amd_ht_init()
AMD_CB_EventNotify()
event class: 05
event: 2006
data: 04 00 00 00
Exit amd_ht_init()
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
F3x80: e600a681
F3x84: a0e641e6
F3xD4: c8810f25
F3xD8: 03000714
F3xDC: 0000522c
core0 started:
start_other_cores()
init node: 00 cores: 00
started ap apicid:
rs780_early_setup()
get_cpu_rev EAX=0x100f63.
CPU Rev is K8_10.
fam10_optimization()
rs780_por_init
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-18-0
sb700_pmio_por_init()
Begin FIDVID MSR 0xc0010071 0x28a40112 0x44025840
FIDVID on BSP, APIC_id: 00
BSP fid = 10500
common_fid = 10500
FID Change Node:00, F3xD4: c8810f25
End FIDVIDMSR 0xc0010071 0x28a40112 0x44025840
rs780_htinit cpu_ht_freq=a.
rs780_htinit: HT3 mode
...WARM RESET...
coreboot-4.0-r759M Mon Jul 19 16:15:56 CST 2010 starting...
BSP Family_Model: 00100f63
*sysinfo range: [000cc000,000cf360]
bsp_apicid = 00
cpu_init_detectedx = 00000000
microcode: equivalent rev id = 0x1043, current patch id = 0x00000000
microcode: patch id to apply = 0x010000b6
microcode: updated to patch id = 0x010000b6 success
cpuSetAMDMSR done
Enter amd_ht_init()
AMD_CB_EventNotify()
event class: 05
event: 2006
data: 04 00 00 00
Exit amd_ht_init()
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
F3x80: e600a681
F3x84: a0e641e6
F3xD4: c8810f25
F3xD8: 03000714
F3xDC: 0000522c
core0 started:
start_other_cores()
init node: 00 cores: 00
started ap apicid:
rs780_early_setup()
get_cpu_rev EAX=0x100f63.
CPU Rev is K8_10.
fam10_optimization()
rs780_por_init
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-18-0
sb700_pmio_por_init()
Begin FIDVID MSR 0xc0010071 0x28a40112 0x44025840
End FIDVIDMSR 0xc0010071 0x28a40112 0x44004402
rs780_htinit cpu_ht_freq=a.
rs780_htinit: HT3 mode
fill_mem_ctrl()
raminit_amdmct()
raminit_amdmct begin:
DIMMPresence: DIMMValid=2
DIMMPresence: DIMMPresent=2
DIMMPresence: RegDIMMPresent=0
DIMMPresence: DimmECCPresent=0
DIMMPresence: DimmPARPresent=0
DIMMPresence: Dimmx4Present=0
DIMMPresence: Dimmx8Present=2
DIMMPresence: Dimmx16Present=0
DIMMPresence: DimmPlPresent=0
DIMMPresence: DimmDRPresent=0
DIMMPresence: DimmQRPresent=0
DIMMPresence: DATAload[0]=0
DIMMPresence: MAload[0]=0
DIMMPresence: MAdimms[0]=0
DIMMPresence: DATAload[1]=1
DIMMPresence: MAload[1]=8
DIMMPresence: MAdimms[1]=1
DIMMPresence: Status 1000
DIMMPresence: ErrStatus 0
DIMMPresence: ErrCode 0
DIMMPresence: Done
DCTInit_D: mct_DIMMPresence Done
SPDCalcWidth: Status 1000
SPDCalcWidth: ErrStatus 0
SPDCalcWidth: ErrCode 0
SPDCalcWidth: Done
DCTInit_D: mct_SPDCalcWidth Done
SPDGetTCL_D: DIMMCASL 4
SPDGetTCL_D: DIMMAutoSpeed 4
SPDGetTCL_D: Status 1000
SPDGetTCL_D: ErrStatus 0
SPDGetTCL_D: ErrCode 0
SPDGetTCL_D: Done
AutoCycTiming: Status 1000
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 2
AutoCycTiming: Done
DCTInit_D: mct_DIMMPresence Done
SPDCalcWidth: Status 1000
SPDCalcWidth: ErrStatus 0
SPDCalcWidth: ErrCode 0
SPDCalcWidth: Done
DCTInit_D: mct_SPDCalcWidth Done
AutoCycTiming: Status 1000
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 0
AutoCycTiming: Done
DCTInit_D: AutoCycTiming_D Done
SPDSetBanks: CSPresent 1
SPDSetBanks: Status 1000
SPDSetBanks: ErrStatus 0
SPDSetBanks: ErrCode 0
SPDSetBanks: Done
AfterStitch pDCTstat->NodeSysBase = 0
mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3fffff
StitchMemory: Status 1000
StitchMemory: ErrStatus 0
StitchMemory: ErrCode 0
StitchMemory: Done
InterleaveBanks_D: Status 1000
InterleaveBanks_D: ErrStatus 80
InterleaveBanks_D: ErrCode 0
InterleaveBanks_D: Done
AutoConfig_D: DramControl: 2a06
AutoConfig_D: DramTimingLo: a0092
AutoConfig_D: DramConfigMisc: 0
AutoConfig_D: DramConfigMisc2: 0
AutoConfig_D: DramConfigLo: 8010000
AutoConfig_D: DramConfigHi: f48000b
AutoConfig: Status 1000
AutoConfig: ErrStatus 80
AutoConfig: ErrCode 0
AutoConfig: Done
DCTInit_D: AutoConfig_D Done
DCTInit_D: PlatformSpec_D Done
DCTInit_D: StartupDCT_D
mctAutoInitMCT_D: SyncDCTsReady_D
mctAutoInitMCT_D: HTMemMapInit_D
Node: 00 base: 00 limit: 3fffff BottomIO: e00000
Node: 00 base: 03 limit: 3fffff
Node: 01 base: 00 limit: 00
Node: 02 base: 00 limit: 00
Node: 03 base: 00 limit: 00
Node: 04 base: 00 limit: 00
Node: 05 base: 00 limit: 00
Node: 06 base: 00 limit: 00
Node: 07 base: 00 limit: 00
mctAutoInitMCT_D: CPUMemTyping_D
CPUMemTyping: Cache32bTOP:400000
CPUMemTyping: Bottom32bIO:400000
CPUMemTyping: Bottom40bIO:0
mctAutoInitMCT_D: DQSTiming_D
TrainRcvrEn: Status 1000
TrainRcvrEn: ErrStatus 80
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done
TrainDQSRdWrPos: Status 1000
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 80
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
TrainDQSRdWrPos: Status 1000
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 80
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
TrainDQSRdWrPos: Status 1000
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 80
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
TrainDQSRdWrPos: Status 1000
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 80
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
mctAutoInitMCT_D: UMAMemTyping_D
mctAutoInitMCT_D: :OtherTiming
InterleaveNodes_D: Status 1000
InterleaveNodes_D: ErrStatus 80
InterleaveNodes_D: ErrCode 0
InterleaveNodes_D: Done
InterleaveChannels_D: Node 0
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 80
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 1
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 2
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 3
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 4
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 5
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 6
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 7
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Done
mctAutoInitMCT_D: ECCInit_D
All Done
raminit_amdmct end:
*** Yes, the copy/decompress is taking a while, FIXME!
v_esp=000cbf48
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now
Clearing initial memory region: Done
Loading stage image.
Check CBFS header at fffffd2e
magic is 4f524243
Found CBFS header at fffffd2e
Check fallback/romstage
CBFS: follow chain: fff00000 + 38 + 17191 + align -> fff17200
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x200000 (1245184 bytes), entry @ 0x200000
CBFS: got here src=fff17254,dest=200000,len=30000
coreboot-4.0-r759M Mon Jul 19 16:15:56 CST 2010 starting...
BSP Family_Model: 00100f63
*sysinfo range: [000cc000,000cf360]
bsp_apicid = 00
cpu_init_detectedx = 00000000
microcode: equivalent rev id = 0x1043, current patch id = 0x00000000
microcode: patch id to apply = 0x010000b6
microcode: updated to patch id = 0x010000b6 success
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