[coreboot] [commit] r5658 - in trunk/src: cpu/amd/model_10xxx cpu/amd/model_fxx include/cpu/amd northbridge/amd/amdk8 southbridge/amd/rs780 southbridge/amd/sb600 southbridge/amd/sb700
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Wed Jul 7 23:59:07 CEST 2010
Author: stepan
Date: Wed Jul 7 23:59:06 2010
New Revision: 5658
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5658
Log:
fix some more warnings
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>
Modified:
trunk/src/cpu/amd/model_10xxx/init_cpus.c
trunk/src/cpu/amd/model_fxx/init_cpus.c
trunk/src/include/cpu/amd/multicore.h
trunk/src/northbridge/amd/amdk8/amdk8.h
trunk/src/northbridge/amd/amdk8/amdk8_f.h
trunk/src/northbridge/amd/amdk8/amdk8_pre_f.h
trunk/src/northbridge/amd/amdk8/coherent_ht.c
trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c
trunk/src/northbridge/amd/amdk8/setup_resource_map.c
trunk/src/southbridge/amd/rs780/rs780_gfx.c
trunk/src/southbridge/amd/sb600/sb600_smbus.c
trunk/src/southbridge/amd/sb600/sb600_smbus.h
trunk/src/southbridge/amd/sb700/sb700.h
trunk/src/southbridge/amd/sb700/sb700_early_setup.c
trunk/src/southbridge/amd/sb700/sb700_smbus.c
trunk/src/southbridge/amd/sb700/sb700_smbus.h
Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c
==============================================================================
--- trunk/src/cpu/amd/model_10xxx/init_cpus.c Wed Jul 7 19:51:41 2010 (r5657)
+++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Wed Jul 7 23:59:06 2010 (r5658)
@@ -244,7 +244,7 @@
}
}
-static void wait_all_other_cores_started(u32 bsp_apicid)
+void wait_all_other_cores_started(u32 bsp_apicid)
{
// all aps other than core0
printk(BIOS_DEBUG, "started ap apicid: ");
Modified: trunk/src/cpu/amd/model_fxx/init_cpus.c
==============================================================================
--- trunk/src/cpu/amd/model_fxx/init_cpus.c Wed Jul 7 19:51:41 2010 (r5657)
+++ trunk/src/cpu/amd/model_fxx/init_cpus.c Wed Jul 7 23:59:06 2010 (r5658)
@@ -178,12 +178,12 @@
}
}
-static void wait_all_aps_started(u32 bsp_apicid)
+void wait_all_aps_started(u32 bsp_apicid)
{
for_each_ap(bsp_apicid, 0, wait_ap_started, (void *)0);
}
-static void wait_all_other_cores_started(u32 bsp_apicid)
+void wait_all_other_cores_started(u32 bsp_apicid)
{
// all aps other than core0
printk(BIOS_DEBUG, "started ap apicid: ");
Modified: trunk/src/include/cpu/amd/multicore.h
==============================================================================
--- trunk/src/include/cpu/amd/multicore.h Wed Jul 7 19:51:41 2010 (r5657)
+++ trunk/src/include/cpu/amd/multicore.h Wed Jul 7 23:59:06 2010 (r5658)
@@ -38,6 +38,9 @@
struct device;
u32 get_apicid_base(u32 ioapic_num);
void amd_sibling_init(struct device *cpu);
+#else
+void wait_all_other_cores_started(u32 bsp_apicid);
+void wait_all_aps_started(u32 bsp_apicid);
#endif
#endif /* CPU_AMD_QUADCORE_H */
Modified: trunk/src/northbridge/amd/amdk8/amdk8.h
==============================================================================
--- trunk/src/northbridge/amd/amdk8/amdk8.h Wed Jul 7 19:51:41 2010 (r5657)
+++ trunk/src/northbridge/amd/amdk8/amdk8.h Wed Jul 7 23:59:06 2010 (r5658)
@@ -8,8 +8,9 @@
#include "amdk8_pre_f.h"
#endif
-#ifndef __ROMCC__
+#ifdef __PRE_RAM__
void showallroutes(int level, device_t dev);
+void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base);
#endif
#endif /* AMDK8_H */
Modified: trunk/src/northbridge/amd/amdk8/amdk8_f.h
==============================================================================
--- trunk/src/northbridge/amd/amdk8/amdk8_f.h Wed Jul 7 19:51:41 2010 (r5657)
+++ trunk/src/northbridge/amd/amdk8/amdk8_f.h Wed Jul 7 23:59:06 2010 (r5658)
@@ -1,6 +1,6 @@
#ifndef AMDK8_F_H
-
#define AMDK8_F_H
+
/* Definitions of various K8 registers */
/* Function 0 */
#define HT_TRANSACTION_CONTROL 0x68
Modified: trunk/src/northbridge/amd/amdk8/amdk8_pre_f.h
==============================================================================
--- trunk/src/northbridge/amd/amdk8/amdk8_pre_f.h Wed Jul 7 19:51:41 2010 (r5657)
+++ trunk/src/northbridge/amd/amdk8/amdk8_pre_f.h Wed Jul 7 23:59:06 2010 (r5658)
@@ -1,5 +1,4 @@
#ifndef AMDK8_PRE_F_H
-
#define AMDK8_PRE_F_H
/* Definitions of various K8 registers */
Modified: trunk/src/northbridge/amd/amdk8/coherent_ht.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/coherent_ht.c Wed Jul 7 19:51:41 2010 (r5657)
+++ trunk/src/northbridge/amd/amdk8/coherent_ht.c Wed Jul 7 23:59:06 2010 (r5658)
@@ -206,12 +206,12 @@
print_spew(" done.\n");
}
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
static void fill_row(u8 node, u8 row, u32 value)
{
pci_write_config32(NODE_HT(node), 0x40+(row<<2), value);
}
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
static u8 link_to_register(int ldt)
{
/*
@@ -447,28 +447,33 @@
}
#if CROSS_BAR_47_56
-static void opt_broadcast_rt(u8 source, u8 dest, u8 kickout) {
+static void opt_broadcast_rt(u8 source, u8 dest, u8 kickout)
+{
uint32_t val;
val = get_row(source, dest);
val -= link_connection(source, kickout)<<16;
fill_row(source, dest, val);
}
-static void opt_broadcast_rt_group(const u8 *conn, int num) {
+static void opt_broadcast_rt_group(const u8 *conn, int num)
+{
int i;
for(i=0; i<num; i+=3) {
opt_broadcast_rt(conn[i], conn[i+1],conn[i+2]);
}
}
-static void opt_broadcast_rt_plus(u8 source, u8 dest, u8 kickout) {
+
+static void opt_broadcast_rt_plus(u8 source, u8 dest, u8 kickout)
+{
uint32_t val;
val = get_row(source, dest);
val += link_connection(source, kickout)<<16;
fill_row(source, dest, val);
}
-static void opt_broadcast_rt_plus_group(const u8 *conn, int num) {
+static void opt_broadcast_rt_plus_group(const u8 *conn, int num)
+{
int i;
for(i=0; i<num; i+=3) {
@@ -477,27 +482,22 @@
}
#endif
-static void setup_row_direct(u8 source, u8 dest, u8 linkn){
+static void setup_row_direct(u8 source, u8 dest, u8 linkn)
+{
setup_row_direct_x(source, source, dest, linkn);
}
-static void setup_remote_row_direct(u8 source, u8 dest, u8 linkn){
+static void setup_remote_row_direct(u8 source, u8 dest, u8 linkn)
+{
setup_row_direct_x(7, source, dest, linkn);
}
static void setup_temp_row(u8 source, u8 dest)
{
- /* copy val from (source, dest) to (source,7) */
- fill_row(source,7,get_row(source,dest));
+ /* copy value from (source, dest) to (source,7) */
+ fill_row(source, 7, get_row(source, dest));
}
-#if 0
-static void clear_temp_row(u8 source)
-{
- fill_row(source, 7, DEFAULT);
-}
-#endif
-
static void setup_remote_node(u8 node)
{
static const uint8_t pci_reg[] = {
@@ -670,7 +670,8 @@
}
#if CONFIG_MAX_PHYSICAL_CPUS > 2
-static int optimize_connection_group(const u8 *opt_conn, int num) {
+static int optimize_connection_group(const u8 *opt_conn, int num)
+{
int needs_reset = 0;
int i;
for(i=0; i<num; i+=2) {
Modified: trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c Wed Jul 7 19:51:41 2010 (r5657)
+++ trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c Wed Jul 7 23:59:06 2010 (r5658)
@@ -1717,6 +1717,7 @@
return reg;
}
+#if CONFIG_MEM_TRAIN_SEQ == 1
static void set_top_mem_ap(unsigned tom_k, unsigned tom2_k)
{
msr_t msr;
@@ -1730,6 +1731,7 @@
msr.hi = (tom_k & 0xffc00000) >> 22;
wrmsr(TOP_MEM, msr);
}
+#endif
static void setup_mtrr_dqs(unsigned tom_k, unsigned tom2_k)
{
@@ -1802,6 +1804,7 @@
}
+#if CONFIG_MEM_TRAIN_SEQ == 1
static unsigned get_htic_bit(unsigned i, unsigned bit)
{
uint32_t dword;
@@ -1816,6 +1819,7 @@
if(get_htic_bit(0, 9)) return;
}
}
+#endif
static void set_sysinfo_in_ram(unsigned val)
{
Modified: trunk/src/northbridge/amd/amdk8/setup_resource_map.c
==============================================================================
--- trunk/src/northbridge/amd/amdk8/setup_resource_map.c Wed Jul 7 19:51:41 2010 (r5657)
+++ trunk/src/northbridge/amd/amdk8/setup_resource_map.c Wed Jul 7 23:59:06 2010 (r5658)
@@ -1,6 +1,8 @@
+#include "amdk8.h"
+
#define RES_DEBUG 0
-static void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base)
+void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base)
{
int i;
#if RES_DEBUG
Modified: trunk/src/southbridge/amd/rs780/rs780_gfx.c
==============================================================================
--- trunk/src/southbridge/amd/rs780/rs780_gfx.c Wed Jul 7 19:51:41 2010 (r5657)
+++ trunk/src/southbridge/amd/rs780/rs780_gfx.c Wed Jul 7 23:59:06 2010 (r5658)
@@ -96,33 +96,33 @@
MMIORANGE MMIO[8], CreativeMMIO[8];
+#define CIM_STATUS u32
+#define CIM_SUCCESS 0x00000000
+#define CIM_ERROR 0x80000000
+#define CIM_UNSUPPORTED 0x80000001
+#define CIM_DISABLEPORT 0x80000002
+
+#define MMIO_ATTRIB_NP_ONLY 1
+#define MMIO_ATTRIB_BOTTOM_TO_TOP 1<<1
+#define MMIO_ATTRIB_SKIP_ZERO 1<<2
+
+#ifdef DONT_TRUST_RESOURCE_ALLOCATION
static MMIORANGE* AllocMMIO(MMIORANGE* pMMIO)
{
int i;
- for (i=0; i<8; i++)
- {
+ for (i=0; i<8; i++) {
if (pMMIO[i].Limit == 0)
return &pMMIO[i];
}
return 0;
}
+
static void FreeMMIO(MMIORANGE* pMMIO)
{
pMMIO->Base = 0;
pMMIO->Limit = 0;
}
-#define CIM_STATUS u32
-#define CIM_SUCCESS 0x00000000
-#define CIM_ERROR 0x80000000
-#define CIM_UNSUPPORTED 0x80000001
-#define CIM_DISABLEPORT 0x80000002
-
-#define MMIO_ATTRIB_NP_ONLY 1
-#define MMIO_ATTRIB_BOTTOM_TO_TOP 1<<1
-#define MMIO_ATTRIB_SKIP_ZERO 1<<2
-
-#ifdef DONT_TRUST_RESOURCE_ALLOCATION
static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
{
int i;
@@ -584,7 +584,6 @@
{
u32 l_dword;
int i;
- device_t k8_f0 = 0, k8_f2 = 0;
device_t nb_dev = dev_find_slot(0, 0);
msr_t sysmem;
@@ -617,7 +616,7 @@
/* LPC DMA Deadlock workaround? */
/* GFX_InitCommon*/
- k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+ device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
l_dword = pci_read_config32(k8_f0, 0x68);
l_dword &= ~(3 << 21);
l_dword |= (1 << 21);
@@ -632,7 +631,7 @@
#if (CONFIG_GFXUMA == 1)
/* GFX_InitUMA. */
/* Copy CPU DDR Controller to NB MC. */
- k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+ device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
for (i = 0; i < 12; i++)
{
l_dword = pci_read_config32(k8_f2, 0x40 + i * 4);
Modified: trunk/src/southbridge/amd/sb600/sb600_smbus.c
==============================================================================
--- trunk/src/southbridge/amd/sb600/sb600_smbus.c Wed Jul 7 19:51:41 2010 (r5657)
+++ trunk/src/southbridge/amd/sb600/sb600_smbus.c Wed Jul 7 23:59:06 2010 (r5658)
@@ -60,7 +60,7 @@
return -3; /* timeout */
}
-static int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
+int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
{
u8 byte;
@@ -87,8 +87,7 @@
return byte;
}
-static int do_smbus_send_byte(u32 smbus_io_base, u32 device,
- u8 val)
+int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
{
u8 byte;
Modified: trunk/src/southbridge/amd/sb600/sb600_smbus.h
==============================================================================
--- trunk/src/southbridge/amd/sb600/sb600_smbus.h Wed Jul 7 19:51:41 2010 (r5657)
+++ trunk/src/southbridge/amd/sb600/sb600_smbus.h Wed Jul 7 23:59:06 2010 (r5658)
@@ -20,8 +20,6 @@
#ifndef SB600_SMBUS_H
#define SB600_SMBUS_H
-//#include <stdint.h>
-
#define SMBHSTSTAT 0x0
#define SMBSLVSTAT 0x1
#define SMBHSTCTRL 0x2
@@ -58,6 +56,8 @@
#define axindxp_reg(reg, mask, val) \
alink_ax_indx(1, (reg), (mask), (val))
+int do_smbus_recv_byte(u32 smbus_io_base, u32 device);
+int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val);
int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
Modified: trunk/src/southbridge/amd/sb700/sb700.h
==============================================================================
--- trunk/src/southbridge/amd/sb700/sb700.h Wed Jul 7 19:51:41 2010 (r5657)
+++ trunk/src/southbridge/amd/sb700/sb700.h Wed Jul 7 23:59:06 2010 (r5658)
@@ -49,4 +49,9 @@
void sb700_enable(device_t dev);
+#ifdef __PRE_RAM__
+void sb700_lpc_port80(void);
+void sb700_pci_port80(void);
+#endif
+
#endif /* SB700_H */
Modified: trunk/src/southbridge/amd/sb700/sb700_early_setup.c
==============================================================================
--- trunk/src/southbridge/amd/sb700/sb700_early_setup.c Wed Jul 7 19:51:41 2010 (r5657)
+++ trunk/src/southbridge/amd/sb700/sb700_early_setup.c Wed Jul 7 23:59:06 2010 (r5658)
@@ -231,7 +231,7 @@
outb(0x06, 0x0cf9);
}
-static void sb700_pci_port80(void)
+void sb700_pci_port80(void)
{
u8 byte;
device_t dev;
@@ -276,7 +276,7 @@
pci_write_config8(dev, 0x4A, byte);
}
-static void sb700_lpc_port80(void)
+void sb700_lpc_port80(void)
{
u8 byte;
device_t dev;
Modified: trunk/src/southbridge/amd/sb700/sb700_smbus.c
==============================================================================
--- trunk/src/southbridge/amd/sb700/sb700_smbus.c Wed Jul 7 19:51:41 2010 (r5657)
+++ trunk/src/southbridge/amd/sb700/sb700_smbus.c Wed Jul 7 23:59:06 2010 (r5658)
@@ -63,7 +63,7 @@
return -3; /* timeout */
}
-static int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
+int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
{
u8 byte;
@@ -90,7 +90,7 @@
return byte;
}
-static int do_smbus_send_byte(u32 smbus_io_base, u32 device,
+int do_smbus_send_byte(u32 smbus_io_base, u32 device,
u8 val)
{
u8 byte;
Modified: trunk/src/southbridge/amd/sb700/sb700_smbus.h
==============================================================================
--- trunk/src/southbridge/amd/sb700/sb700_smbus.h Wed Jul 7 19:51:41 2010 (r5657)
+++ trunk/src/southbridge/amd/sb700/sb700_smbus.h Wed Jul 7 23:59:06 2010 (r5658)
@@ -56,6 +56,8 @@
#define axindxp_reg(reg, mask, val) \
alink_ax_indx(1, (reg), (mask), (val))
+int do_smbus_recv_byte(u32 smbus_io_base, u32 device);
+int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val);
int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
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