[coreboot] [commit] r5059 - in trunk/src: northbridge/amd/lx southbridge/amd/cs5536

svn at coreboot.org svn at coreboot.org
Wed Jan 27 20:20:30 CET 2010


Author: oxygene
Date: 2010-01-27 20:20:29 +0100 (Wed, 27 Jan 2010)
New Revision: 5059

Modified:
   trunk/src/northbridge/amd/lx/Kconfig
   trunk/src/northbridge/amd/lx/grphinit.c
   trunk/src/northbridge/amd/lx/northbridgeinit.c
   trunk/src/southbridge/amd/cs5536/Kconfig
Log:
Add the MSR writes that are needed to provide VGA legacy routing for the Geode LX
Add appropriate Kconfig defines to provide 8mb of VGA ram allocation
Add the Kconfig defines to cover TSC calibration from TIMER2 and UDELAY setup
Two small warning removals about excessive prototyping.

Signed-off-by: Edwin Beasant <edwin_beasant at virtensys.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Modified: trunk/src/northbridge/amd/lx/Kconfig
===================================================================
--- trunk/src/northbridge/amd/lx/Kconfig	2010-01-27 18:19:33 UTC (rev 5058)
+++ trunk/src/northbridge/amd/lx/Kconfig	2010-01-27 19:20:29 UTC (rev 5059)
@@ -1,4 +1,8 @@
 config NORTHBRIDGE_AMD_LX
 	bool
 	select HAVE_HIGH_TABLES
-
+	
+config VIDEO_MB
+	int
+	default 8
+	depends on NORTHBRIDGE_AMD_LX

Modified: trunk/src/northbridge/amd/lx/grphinit.c
===================================================================
--- trunk/src/northbridge/amd/lx/grphinit.c	2010-01-27 18:19:33 UTC (rev 5058)
+++ trunk/src/northbridge/amd/lx/grphinit.c	2010-01-27 19:20:29 UTC (rev 5059)
@@ -22,7 +22,46 @@
 #include <stdint.h>
 #include <cpu/amd/vr.h>
 #include <console/console.h>
+#include <cpu/amd/lxdef.h>
+#include <cpu/x86/msr.h>
+#include <stdlib.h>
 
+void geodelx_vga_msr_init(void);
+void graphics_init(void);
+
+struct msrinit {
+	u32 msrnum;
+	msr_t msr;
+};
+
+static const struct msrinit geodelx_vga_msr[] = {
+	/* Enable the GLIU Memory routing to the hardware 
+	* PDID1 : Port 4, GLIU0
+	* PBASE : 0x000A0
+	* PMASK : 0xFFFE0
+	*/
+	{.msrnum = MSR_GLIU0_BASE4, {.lo = 0x0a0fffe0, .hi = 0x80000000}},
+	/* Enable the GLIU IO Routing
+	* IDID  : Port 4, GLIU0
+	* IBASE : 0x003c0
+	* IMASK : 0xffff0
+	*/
+	{.msrnum = GLIU0_IOD_BM_0,  {.lo = 0x3c0ffff0, .hi = 0x80000000}},
+	/* Enable the GLIU IO Routing
+	* IDID  : Port 4, GLIU0
+	* IBASE : 0x003d0
+	* IMASK : 0xffff0
+	*/
+	{.msrnum = GLIU0_IOD_BM_1,  {.lo = 0x3d0ffff0, .hi = 0x80000000}},
+};
+
+void geodelx_vga_msr_init(void)
+{
+	int i;
+	for (i = 0; i < ARRAY_SIZE(geodelx_vga_msr); i++)
+		wrmsr(geodelx_vga_msr[i].msrnum, geodelx_vga_msr[i].msr);
+}
+
  /*
   * This function mirrors the Graphics_Init routine in GeodeROM.
   */
@@ -32,7 +71,9 @@
 
 	/* SoftVG initialization */
 	printk_debug("Graphics init...\n");
-
+   
+	geodelx_vga_msr_init();
+   
 	/* Call SoftVG with the main configuration parameters. */
 	/* NOTE: SoftVG expects the memory size to be given in 2MB blocks */
 

Modified: trunk/src/northbridge/amd/lx/northbridgeinit.c
===================================================================
--- trunk/src/northbridge/amd/lx/northbridgeinit.c	2010-01-27 18:19:33 UTC (rev 5058)
+++ trunk/src/northbridge/amd/lx/northbridgeinit.c	2010-01-27 19:20:29 UTC (rev 5059)
@@ -99,7 +99,6 @@
 	{0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}},	/*  END */
 };
 
-extern int sizeram(void);
 
 static void writeglmsr(struct gliutable *gl)
 {
@@ -122,7 +121,6 @@
 	}
 }
 
-extern int sizeram(void);
 static void SysmemInit(struct gliutable *gl)
 {
 	msr_t msr;
@@ -749,7 +747,6 @@
 /* ***************************************************************************/
 void northbridge_init_early(void)
 {
-	msr_t msr;
 	int i;
 	printk_debug("Enter %s\n", __func__);
 

Modified: trunk/src/southbridge/amd/cs5536/Kconfig
===================================================================
--- trunk/src/southbridge/amd/cs5536/Kconfig	2010-01-27 18:19:33 UTC (rev 5058)
+++ trunk/src/southbridge/amd/cs5536/Kconfig	2010-01-27 19:20:29 UTC (rev 5059)
@@ -20,3 +20,12 @@
 config SOUTHBRIDGE_AMD_CS5536
 	bool
 
+select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+
+config UDELAY_TSC
+	bool
+	default y
+	depends on SOUTHBRIDGE_AMD_CS5536
+
+	
+





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