[coreboot] KBuild Report [r5026]
coresystems autobuild service
svn at coresystems.de
Sun Jan 17 17:01:50 CET 2010
[1/116] a-trend/atc-6220 ok.
Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[2/116] a-trend/atc-6240 ok.
Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[3/116] abit/be6-ii_v2_0 ok.
Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[4/116] advantech/pcm-5820 ok.
Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[5/116] amd/db800 ok.
Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x4
+CONFIG_IRQ_SLOT_COUNT = 0x6
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[6/116] amd/dbm690t ok.
Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/amd/dbm690t/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_ROM_SIZE = 0x100000
+CONFIG_ROM_SIZE = 0x80000
[7/116] amd/norwich ok.
Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[8/116] amd/pistachio ok.
Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/amd/pistachio/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x8
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x0
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_ROM_SIZE = 0x100000
+CONFIG_ROM_SIZE = 0x80000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[9/116] amd/rumba ok.
Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[10/116] amd/serengeti_cheetah ok.
Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/amd/serengeti_cheetah/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_ACPI_SSDTX_NUM = 0x1
+CONFIG_ACPI_SSDTX_NUM = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[11/116] amd/serengeti_cheetah_fam10 ok.
Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[12/116] arima/hdama ok.
Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/arima/hdama/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[13/116] artecgroup/dbe61 ok.
Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[14/116] asi/mb_5blgp ok.
Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[15/116] asi/mb_5blmp ok.
Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[16/116] asus/a8n_e ok.
Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/asus/a8n_e/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xc8000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[17/116] asus/a8v-e_se ok.
Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_IRQ_SLOT_COUNT = 0xd
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[18/116] asus/m2v-mx_se ok.
Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/asus/m2v-mx_se/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
-CONFIG_HAVE_ACPI_RESUME = 0x1
+CONFIG_HAVE_ACPI_RESUME = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_LOW_TABLES = 0x0
+CONFIG_HAVE_LOW_TABLES = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x1f00000
+CONFIG_RAMBASE = 0x100000
-CONFIG_RAMTOP = 0x2000000
+CONFIG_RAMTOP = 0x200000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[19/116] asus/mew-am ok.
Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[20/116] asus/mew-vm ok.
Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[21/116] asus/p2b-d ok.
Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[22/116] asus/p2b-ds ok.
Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_AGP_APERTURE_SIZE = 0x4000000
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_ADDR_BITS = 0x24
+CONFIG_CPU_ADDR_BITS = 0x28
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xc0000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_ID_SECTION_OFFSET = 0x10
+CONFIG_ID_SECTION_OFFSET = 0x80
-CONFIG_IRQ_SLOT_COUNT = 0x7
+CONFIG_IRQ_SLOT_COUNT = 0xd
-CONFIG_LB_CKS_LOC = 0x7e
+CONFIG_LB_CKS_LOC = 0x7b
-CONFIG_LB_CKS_RANGE_END = 0x7d
+CONFIG_LB_CKS_RANGE_END = 0x7a
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_MEM_TRAIN_SEQ = 0x0
+CONFIG_MEM_TRAIN_SEQ = 0x2
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_ROM_SIZE = 0x40000
+CONFIG_ROM_SIZE = 0x80000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_USE_DCACHE_RAM = 0x0
+CONFIG_USE_DCACHE_RAM = 0x1
-CONFIG_USE_PRINTK_IN_CAR = 0x0
+CONFIG_USE_PRINTK_IN_CAR = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[23/116] asus/p2b-f ok.
Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[24/116] asus/p2b ok.
Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[25/116] asus/p3b-f ok.
Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[26/116] axus/tc320 ok.
Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[27/116] azza/pt-6ibd ok.
Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[28/116] bcom/winnet100 ok.
Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[29/116] bcom/winnetp680 fail.
[30/116] biostar/m6tba ok.
Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[31/116] broadcom/blast ok.
Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x6
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[32/116] compaq/deskpro_en_sff_p600 ok.
Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[33/116] dell/s1850 fail.
[34/116] digitallogic/adl855pc ok.
Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SMP = 0x0
+CONFIG_SMP = 0x1
-CONFIG_UDELAY_IO = 0x1
+CONFIG_UDELAY_IO = 0x0
-CONFIG_UDELAY_TSC = 0x0
+CONFIG_UDELAY_TSC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[35/116] digitallogic/msm586seg ok.
Processing mainboard/digitallogic/msm586seg (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/digitallogic/msm586seg/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_AMD_SC520 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_ROM_SIZE = 0x80000
+CONFIG_ROM_SIZE = 0x40000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_UDELAY_LAPIC = 0x0
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[36/116] digitallogic/msm800sev ok.
Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x9
+CONFIG_IRQ_SLOT_COUNT = 0x7
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[37/116] eaglelion/5bcm ok.
Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[38/116] emulation/qemu-x86 ok.
Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/emulation/qemu-x86/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_EMULATION_QEMU_X86 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0x8f000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_UDELAY_LAPIC = 0x0
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[39/116] gigabyte/ga-6bxc ok.
Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x6
+CONFIG_IRQ_SLOT_COUNT = 0x5
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[40/116] gigabyte/ga_2761gxdk ok.
Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x16
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_MEM_TRAIN_SEQ = 0x2
+CONFIG_MEM_TRAIN_SEQ = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[41/116] gigabyte/m57sli ok.
Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/gigabyte/m57sli/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x16
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_MEM_TRAIN_SEQ = 0x2
+CONFIG_MEM_TRAIN_SEQ = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[42/116] hp/dl145_g3 ok.
Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x8
+CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x6
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[43/116] hp/e_vectra_p2706t ok.
Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
[44/116] ibm/e325 ok.
Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x8
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[45/116] ibm/e326 ok.
Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/ibm/e326/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x8
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[46/116] iei/juki-511p ok.
Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/iei/juki-511p/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_INIT_TIMER = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_UDELAY_IO = 0x1
+CONFIG_UDELAY_IO = 0x0
-CONFIG_UDELAY_TSC = 0x0
+CONFIG_UDELAY_TSC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[47/116] iei/nova4899r ok.
Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
-CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[48/116] iei/pcisa-lx-800-r10 ok.
Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_UDELAY_IO = 0x1
+CONFIG_UDELAY_IO = 0x0
-CONFIG_UDELAY_TSC = 0x0
+CONFIG_UDELAY_TSC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[49/116] intel/d945gclf fail.
[50/116] intel/eagleheights fail.
[51/116] intel/jarrell fail.
[52/116] intel/mtarvon fail.
[53/116] intel/truxton fail.
[54/116] intel/xe7501devkit ok.
Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[55/116] iwill/dk8_htx ok.
Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/iwill/dk8_htx/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_ACPI_SSDTX_NUM = 0x3
+CONFIG_ACPI_SSDTX_NUM = 0x0
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x8
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xc4000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_SIZE = 0xc000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK = 0x80000
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[56/116] iwill/dk8s2 ok.
Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x8
+CONFIG_ATI_RAGE_XL = 0x1
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_IRQ_SLOT_COUNT = 0xc
+CONFIG_IRQ_SLOT_COUNT = 0xb
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAX_CPUS = 0x2
+CONFIG_MAX_CPUS = 0x4
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[57/116] iwill/dk8x ok.
Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x8
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_IRQ_SLOT_COUNT = 0x9
+CONFIG_IRQ_SLOT_COUNT = 0xb
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAX_CPUS = 0x2
+CONFIG_MAX_CPUS = 0x4
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[58/116] jetway/j7f24 fail.
[59/116] kontron/986lcd-m ok.
Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/kontron/986lcd-m/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
[60/116] kontron/kt690 ok.
Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/kontron/kt690/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_ROM_SIZE = 0x100000
+CONFIG_ROM_SIZE = 0x80000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[61/116] lippert/frontrunner ok.
Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[62/116] lippert/roadrunner-lx ok.
Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[63/116] lippert/spacerunner-lx ok.
Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[64/116] mitac/6513wu ok.
Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[65/116] msi/ms6119 ok.
Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[66/116] msi/ms6147 ok.
Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[67/116] msi/ms6156 ok.
Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[68/116] msi/ms6178 ok.
Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[69/116] msi/ms7135 ok.
Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/msi/ms7135/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_DCACHE_RAM_BASE = 0xc8000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_MEM_TRAIN_SEQ = 0x2
+CONFIG_MEM_TRAIN_SEQ = 0x0
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[70/116] msi/ms7260 ok.
Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/msi/ms7260/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x16
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_MEM_TRAIN_SEQ = 0x2
+CONFIG_MEM_TRAIN_SEQ = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[71/116] msi/ms9185 ok.
Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/msi/ms9185/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x8
+CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x6
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[72/116] msi/ms9282 ok.
Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/msi/ms9282/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x16
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x2
-CONFIG_MAX_PHYSICAL_CPUS = 0x2
+CONFIG_MAX_PHYSICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[73/116] nec/powermate2000 ok.
Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[74/116] newisys/khepri ok.
Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x9
+CONFIG_IRQ_SLOT_COUNT = 0xb
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[75/116] nvidia/l1_2pvv ok.
Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/nvidia/l1_2pvv/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x16
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x2
-CONFIG_MAX_PHYSICAL_CPUS = 0x2
+CONFIG_MAX_PHYSICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[76/116] olpc/btest ok.
Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[77/116] olpc/rev_a ok.
Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[78/116] pcengines/alix1c ok.
Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[79/116] rca/rm4100 ok.
Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/rca/rm4100/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I830_VIDEO_MB_1MB = 0x0
+CONFIG_I830_VIDEO_MB_512KB = 0x0
+CONFIG_I830_VIDEO_MB_8MB = 0x1
+CONFIG_I830_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[80/116] soyo/sy-6ba-plus-iii ok.
Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[81/116] sunw/ultra40 ok.
Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[82/116] supermicro/h8dme ok.
Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/supermicro/h8dme/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_LOW_TABLES = 0x0
+CONFIG_HAVE_LOW_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[83/116] supermicro/h8dmr ok.
Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/supermicro/h8dmr/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_ROM_SIZE = 0x100000
+CONFIG_ROM_SIZE = 0x80000
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[84/116] supermicro/h8dmr_fam10 ok.
Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1511
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x15d9
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[85/116] supermicro/x6dai_g fail.
[86/116] supermicro/x6dhe_g fail.
[87/116] supermicro/x6dhe_g2 fail.
[88/116] supermicro/x6dhr_ig fail.
[89/116] supermicro/x6dhr_ig2 fail.
[90/116] technexion/tim5690 ok.
Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/technexion/tim5690/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
[91/116] technexion/tim8690 ok.
Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/technexion/tim8690/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x8
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x0
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[92/116] technologic/ts5300 ok.
Processing mainboard/technologic/ts5300 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/technologic/ts5300/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_AMD_SC520 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_ROM_SIZE = 0x20000
+CONFIG_ROM_SIZE = 0x40000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
-CONFIG_TTYS0_BASE = 0x2f8
+CONFIG_TTYS0_BASE = 0x3f8
+CONFIG_UDELAY_LAPIC = 0x0
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[93/116] televideo/tc7020 ok.
Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[94/116] thomson/ip1000 ok.
Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/thomson/ip1000/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I830_VIDEO_MB_1MB = 0x0
+CONFIG_I830_VIDEO_MB_512KB = 0x0
+CONFIG_I830_VIDEO_MB_8MB = 0x1
+CONFIG_I830_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[95/116] tyan/s1846 ok.
Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[96/116] tyan/s2735 fail.
[97/116] tyan/s2850 fail.
[98/116] tyan/s2875 ok.
Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[99/116] tyan/s2880 fail.
[100/116] tyan/s2881 fail.
[101/116] tyan/s2882 fail.
[102/116] tyan/s2885 fail.
[103/116] tyan/s2891 ok.
Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/tyan/s2891/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_ROM_SIZE = 0x80000
+CONFIG_ROM_SIZE = 0x100000
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
[104/116] tyan/s2892 ok.
Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/tyan/s2892/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[105/116] tyan/s2895 ok.
Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/tyan/s2895/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
[106/116] tyan/s2912 ok.
Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/tyan/s2912/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_ACPI_SSDTX_NUM = 0x3
+CONFIG_ACPI_SSDTX_NUM = 0x0
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x16
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x2
-CONFIG_MAX_PHYSICAL_CPUS = 0x2
+CONFIG_MAX_PHYSICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[107/116] tyan/s2912_fam10 ok.
Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/tyan/s2912_fam10/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[108/116] tyan/s4880 ok.
Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x16
+CONFIG_IRQ_SLOT_COUNT = 0xb
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_MAX_CPUS = 0x8
+CONFIG_MAX_CPUS = 0x4
-CONFIG_MAX_PHYSICAL_CPUS = 0x4
+CONFIG_MAX_PHYSICAL_CPUS = 0x2
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[109/116] tyan/s4882 ok.
Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x16
+CONFIG_IRQ_SLOT_COUNT = 0xb
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_MAX_CPUS = 0x8
+CONFIG_MAX_CPUS = 0x4
-CONFIG_MAX_PHYSICAL_CPUS = 0x4
+CONFIG_MAX_PHYSICAL_CPUS = 0x2
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x2000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[110/116] via/epia-cn fail.
[111/116] via/epia-m ok.
Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/via/epia-m/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
[112/116] via/epia-m700 ok.
Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/via/epia-m700/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_SIZE = 0x2000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HEAP_SIZE = 0x5000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
[113/116] via/epia-n fail.
[114/116] via/epia ok.
Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[115/116] via/pc2500e fail.
[116/116] via/vt8454c ok.
Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5026/targets/via/vt8454c/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_ROM_SIZE = 0x80000
+CONFIG_ROM_SIZE = 0x100000
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
More information about the coreboot
mailing list