[coreboot] [commit] r5013 - trunk/src/cpu/intel/model_106cx

[svn at coreboot.org]

Author: stepan
Date: 2010-01-16 14:48:20 +0100 (Sat, 16 Jan 2010)
New Revision: 5013

Modified:
   trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c
Log:
Fix stack base for Atom CPUs, the resume mechanism (cbmem etc) expects this.
This unifies the base with Core and Core 2 CPUs.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c
===================================================================
--- trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c	2010-01-16 13:47:07 UTC (rev 5012)
+++ trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c	2010-01-16 13:48:20 UTC (rev 5013)
@@ -87,10 +87,10 @@
 	}
 
 	__asm__ volatile (
-                /* set new esp */ /* before _RAMBASE */
-                "subl   %0, %%ebp\n\t"
-                "subl   %0, %%esp\n\t"
-                ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- CONFIG_RAMBASE )
+                /* set new esp */
+                "movl   %0, %%ebp\n\t"
+                "movl   %0, %%esp\n\t"
+                ::"a"( CONFIG_RAMBASE + (1024-64)*1024 )
 	);
 
 	{