[coreboot] coreboot and MSM800BEV

Fri Jan 15 20:30:42 CET 2010

Piotr Piwko wrote:
> > ./msrtool 0x200000{18,19,1a,1b,1c,1d} 0x4c0000{0f,14}
> 
> OK, here is my output:
> 
> 0x20000018 = 0x1007701400004840
> 0x20000019 = 0x180000006a7332a3
> 0x2000001a = 0x00000000130cd101
> 0x2000001b = 0x0000000000000000
> 0x2000001c = 0x0000000000ff00ff
> 0x2000001d = 0x0000000000001000
> 0x4c00000f = 0x83f100aa569603c4
> 0x4c000014 = 0x0000049c07de000c
> 
> I am going to analyze it ...

If msrtool didn't decode these for you then that's a bug. Did you get
something similar to the following output?

# MC_CF07_DATA 0x20000018 = 0x1007701400004840
# 63:60 D1_SZ DIMM1 Size = 0001: 8 MB
#    56 D1_MB DIMM1 Module Banks = 0: 1 Module bank
#    52 D1_CB DIMM1 Component Banks = 0: 2 Component banks
# 50:48 D1_PSZ DIMM1 Page Size = 111: DIMM1 Not Installed
# 47:44 D0_SZ DIMM0 Size = 0111: 512 MB
#    40 D0_MB DIMM0 Module Banks = 0: 1 Module bank
#    36 D0_CB DIMM0 Component Banks = 1: 4 Component banks
# 34:32 D0_PSZ DIMM0 Page Size = 100: 16 KB
# 29:28 MSR_BA Mode Register Set Bank Address = 00: Program the DIMM Mode Register
#    27 RST_DLL Mode Register Reset DLL = 0: Do not reset DLL
#    26 EMR_QFC Extended Mode Register FET Control = 0: Enable
#    25 EMR_DRV Extended Mode Register Drive Strength Control = 0: Normal
#    24 EMR_DLL Extended Mode Register DLL = 0: Enable
#  23:8 REF_INT Refresh Interval = 72
#   7:4 REF_STAG Refresh Staggering = 4
#     3 REF_TST Test Refresh = 0
#     1 SOFT_RST Software Reset = 0
#     0 PROG_DRAM Program Mode Register in SDRAM = 0

# MC_CF8F_DATA 0x20000019 = 0x180000006a7332a3
# 63:56 STALE_REQ GLIU Max Stale Request Count = 24
# 52:51 XOR_BIT_SEL XOR Bit Select = 00: ADDR[18]
#    50 XOR_MB0 XOR MB0 Enable = 0: Disabled
#    49 XOR_BA1 XOR BA1 Enable = 0: Disabled
#    48 XOR_BA0 XOR BA0 Enable = 0: Disabled
#    41 TRUNC_DIS Burst Truncate Disable = 0: Bursts Enabled
#    40 REORDER_DIS Reorder Disable = 0: Reordering Enabled
#    33 HOI_LOI High / Low Order Interleave Select = 0: Low Order Interleave
#    31 THZ_DLY tHZ Delay = 0
# 30:28 CAS_LAT Read CAS Latency = 110: 2.5
# 27:24 ACT2ACTREF ACT to ACT/REF Period. tRC = 10
# 23:20 ACT2PRE ACT to PRE Period. tRAS = 7
# 18:16 PRE2ACT PRE to ACT Period. tRP = 3
# 14:12 ACT2CMD Delay Time from ACT to Read/Write. tRCD = 3
#  11:8 ACT2ACT ACT(0) to ACT(1) Period. tRRD = 2
#   7:6 DPLWR Data-in to PRE Period. tDPLW = 2: 2
#   5:4 DPLRD Data-in to PRE Period. tDPLR = 2: 2

# MC_CF1017_DATA 0x2000001a = 0x00000000130cd101
# 29:28 WR_TO_RD Write to Read Delay. tWTR = 1
# 26:24 RD_TMG_CTL Read Timing Control = 3
# 20:16 REF2ACT Refresh to Activate Delay. tRFC = 12
#  15:8 PM1_UP_DLY PMode1 Up Delay = 209
#   2:0 WR2DAT Write Command to Data Latency = 1: 1-clock delay for unbuffered DIMMs

# MC_CFPERF_CNT1 0x2000001b = 0x0000000000000000
# 63:32 CNT0 Counter 0 = 0
#  31:0 CNT1 Counter 1 = 0

# MC_PERFCNT2 0x2000001c = 0x0000000000ff00ff
#    35 STOP_CNT1 Stop Counter 1 = 0
#    34 RST_CNT1 Reset Counter 1 = 0
#    33 STOP_CNT0 Stop Counter 0 = 0
#    32 RST_CNT0 Reset Counter 0 = 0

# MC_CFCLK_DBUG 0x2000001d = 0x0000000000001000
#    34 B2B_DIS Back-to-Back Command Disable = 0: Allow back-to-back commands
#    33 MTEST_RBEX_EN MTEST RBEX Enable = 0: Disable
#    32 MTEST_EN MTEST Enable = 0: Disable
#    16 FORCE_PRE Force Precharge-all = 0: Disable
#    12 TRISTATE_DIS TRI-STATE Disable = 1: Tri-stating disabled
#     9 MASK_CKE1 CKE1 Mask = 0: CKE1 output enable unmasked
#     8 MASK_CKE0 CKE0 Mask = 0: CKE0 output enable unmasked
#     7 CNTL_MSK1 Control Mask 1 = 0: DIMM1 CAS1# RAS1# WE1# CS[3:2]# output enable unmasked
#     6 CNTL_MSK0 Control Mask 0 = 0: DIMM0 CAS0# RAS0# WE0# CS[1:0]# output enable unmasked
#     5 ADRS_MSK Address Mask = 0: MA and BA output enable unmasked

# GLCP_DELAY_CONTROLS 0x4c00000f = 0x83f100aa569603c4
#    63 EN Enable = 1: Use value in bits [62:0]
#    62 B_DQ Buffer Control for DQ DQS DQM TLA drive = 0: Quarter power
#    61 B_CMD Buffer Control for RAS CAS CKE CS WE drive = 0: Quarter power
#    60 B_MA Buffer Control for MA BA drive = 0: Half power
#    59 SDCLK_SET SDCLK Setup = 0: Full SDCLK setup
# 58:56 DDR_RLE DDR read latch enable position = 3
#    55 SDCLK_DIS SDCLK disable [1,3,5] = 1: SDCLK[0,2,4] output only
# 54:52 TLA1_OA TLA hint pin output adjust = 7
# 51:50 D_TLA1 Output delay for TLA1 = 0
# 49:48 D_TLA0 Output delay for TLA0 = 1
# 47:46 D_DQ_E Output delay for DQ DQM - even byte lanes = 0
# 45:44 D_DQ_O Output delay for DQ DQM - odd byte lanes = 0
# 41:40 D_SDCLK Output delay for SDCLK = 0
# 39:38 D_CMD_O Output delay for CKE CS RAS CAS WE - odd bits = 2
# 37:36 D_CMD_E Output delay for CKE CS RAS CAS WE - even bits = 2
# 35:34 D_MA_O Output delay for BA MA - odd bits = 2
# 33:32 D_MA_E Output delay for BA MA - even bits = 2
# 31:30 D_PCI_O Output delay for pci_ad IRQ13 SUSPA# INTA# - odd bits = 1
# 29:28 D_PCI_E Output delay for pci_ad IRQ13 SUSPA# INTA# - even bits = 1
# 27:26 D_DOTCLK Output delay for DOTCLK = 1
# 25:24 D_DRGB_O Output delay for DRGB[31:0] - odd bits = 2
# 23:22 D_DRGB_E Output delay for DRGB[31:0] HSYNC VSYNC DISPEN VDDEN LDE_MOD - even bits = 2
# 21:20 D_PCI_IN Input delay for pci_ad CBE# PAR STOP# FRAME# IRDY# TRDY# DEVSEL# REQ# GNT# CIS = 1
# 19:18 D_TDBGI Input delay for TDBGI = 1
# 17:16 D_VIP Input delay for VID[15:0] VIP_HSYNC VIP_VSYNC = 2
# 15:14 D_VIPCLK Input delay for VIPCLK = 0
#    13 H_SDCLK Half SDCLK hold select (for cmd addr) = 0: Full SDCLK setup
# 12:11 PLL_FD_DEL PLL Feedback Delay = 00: No feedback delay
#     5 DLL_OV DLL Override (to DLL) = 0
#   4:0 DLL_OVS/RSDA DLL Override Setting or Read Strobe Delay Adjust = 4

# GLCP_SYS_RSTPLL 0x4c000014 = 0x0000049c07de000c
# 43:39 GLIUMULT GLIU Multiplier = 9
#    38 GLIUDIV GLIU Divide = 0: Do not predivide input
# 37:33 COREMULT CPU Core Multiplier = 14
#    32 COREDIV CPU Core Divide = 0: Do not predivide input
# 31:26 SWFLAGS Flags = 000001
#    25 GLIULOCK GLIU PLL Lock = 1: PLL locked
#    24 CORELOCK CPU Core PLL Lock = 1: PLL locked
# 23:16 HOLD_COUNT Hold Count, divided by 16 = 222
#    14 GLIUPD GLIU PLL Power Down mode = 0
#    13 COREPD CPU Core PLL Power Down mode = 0
#    12 GLIUBYPASS GLIU PLL Bypass = 0: DOTPLL drives the GLIU clock
#    11 COREBYPASS CPU Core PLL Bypass = 0: DOTPLL drives the CPU Core clock
#    10 LPFEN Loop Filter = 0: Disabled
#     9 VA_SEMI_SYNC_MODE CPU-GLIU Sync Mode = 0: The GLIU FIFO is used by the CPU
#     8 PCI_SEMI_SYNC_MODE PCI-GLIU Sync Mode = 0: Falling edges on mb_func_clk and pci_func_clk are used by PCI
#     7 BOOTSTRAP_PW1 PW1 bootstrap = 0: 33MHz PCI clock
#     6 BOOTSTRAP_IRQ13 IRQ13 bootstrap = 0: No stall
#   5:1 BOOTSTRAPS CPU/GLIU frequency select = 00110
#     0 CHIP_RESET Chip Reset = 0

//Peter