[coreboot] coreboot and MSM800BEV

Piotr Piwko piotr.piwko at gmail.com
Fri Jan 8 13:57:51 CET 2010

OK, I removed all references to DIMM1 memory (there is only DIMM0 on
MSM800BEV board)  and the "SMBUS READ ERROR:03 device:a2" error
doesn't occur - please see attached log.

My booting process as previously hangs on "Uncompressing coreboot to
ram". I suppose this situation is related with copying data from cache
into RAM memory in cpu/amd/car/cache_as_ram.inc file, the suitable

----------------- [ cpu/amd/car/cache_as_ram.inc ] -----------------

	 *	Copy data into RAM and clear the BSS. Since these segments
	 *	isn\'t really that big we just copy/clear using bytes, not
	 *	double words.
	intel_chip_post_macro(0x11)		/* post 11 */

	cld				/* clear direction flag */

	/* copy coreboot from it's initial load location to
	 * the location it is compiled to run at.
	 * Normally this is copying from FLASH ROM to RAM.
	movl	%ebp, %esi
	/* FIXME: look for a proper place for the stack */
	movl	$0x4000000, %esp
	movl	%esp, %ebp
	pushl	%esi
	pushl $str_coreboot_ram_name
	call cbfs_and_run_core

It prints $str_coreboot_ram_name ("Uncompressing coreboot to ram") and
hangs after calling cbfs_and_run_core function. I think that I should
set a proper memory address for stack. As we can see the default
address (0x4000000) is wrong but which one is correct? Can you give my
any hints?

Thanks in advance

Piotr Piwko
-------------- next part --------------
coreboot-2.0.0-r4949M.0Fallback pi??, 8 sty 2010, 13:26:09 CET starting...
_MSR GLCP_SYS_RSTPLL (4c000014) value is: 00000392:0000180c
Configuring PLL

coreboot-2.0.0-r4949M.0Fallback pi??, 8 sty 2010, 13:26:09 CET starting...
_MSR GLCP_SYS_RSTPLL (4c000014) value is: 00000392:07de000c
Done pll_reset
Castle 2.0 BTM periodic sync period.
Enable Quack for fewer re-RAS on the MC
 GLIU port active enable
Set the Delay Control in GLCP
Try to write GLCP_DELAY_CONTROLS: hi 83f100aa and lo 56960004
SetDelayControl done
Enable RSDC
FPU imprecise exceptions bit
Enable Suspend on HLT & PAUSE instructions
Enable SUSP and allow TSC to run in Suspend
Setup throttling delays to proper mode
Done cpuRegInit
===========================Check DIMM 0======================================
===========================Check DDR MAX======================================
===========================AUTOSIZE DIMM 0======================================
===========================Check present======================================
===========================BEFORT CTZ======================================
===========================TEST DIMM SIZE>8=====================================
===========================>12address test======================================
===========================RDMSR CF07======================================
===========================WRMSR CF07======================================
===========================ALL DONE======================================
===========================set cas latency======================================
===========================set all latency======================================
===========================set emrs======================================
===========================set ref rate======================================
DRAM controller init done.
RAM DLL lock
Testing DRAM : 00000000 - 000a0000
DRAM fill: 0x00000000-0x000a0000
DRAM filled
DRAM verify: 0x00000000-0x000a0000
DRAM range verified.
Past wbinvd
Uncompressing coreboot to ram.

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