[coreboot] Executing bootstrap from MBR in coreboot

Piotr Piwko piotr.piwko at gmail.com
Thu Feb 25 15:58:25 CET 2010


2010/2/24 Myles Watson <mylesgw at gmail.com>:
> Given the boot logs it's very possible that someone on the list will fix it
> for you.  In most cases it only takes a few iterations.

We were discussing about fixing this coreboot-v3 bug in my previous
thread (http://www.mail-archive.com/coreboot@coreboot.org/msg21110.html)
and I didn't get any positive results. I think that the memory
controller initialization process is not carried out in the proper
way. I've even talked with AMD guys who gave me some hints, but
unfortunately it must be postponed for a while and wait for my free
time.

They have some objections about the following registers:
- MC_CF1017_DATA (0x2000001a) should be equal something more like
0x00000000_140DD101 instead of 0x00000000_00000101
- GLCP_DELAY_CONTROLS (0x4c00000f) should be closer to something like
0xF2F100FF_56960004

Below, there is complete list of registers which are related with
memory controller. Of course, I get it after coreboot-v3 memory
initialization process:

CPU_PF_CONF         (0x00001100): 0x00000100_00005051
GLIU0_ARB           (0x10000082): 0x80000000_00000000
GLIU1_ARB           (0x40000082): 0x80000000_00000000
GLIU1_PORT_ACTIVE   (0x40000081): 0x00000000_0000c77f
CPU_AC_SMM_CTL      (0x00001301): 0x00000000_00000008
CPU_FPU_MSR_MODE    (0x00001a00): 0x00000000_00000001
CPU_XC_CONFIG       (0x00001210): 0x00000000_00000003
CPU_BC_CONF_0       (0x00001900): 0x00000000_02001131
GLCP_DBGCLKCTL      (0x4c000016): 0x00000000_00000002
GLCP_TH_OD          (0x4c00001e): 0x00000000_0000603c
MC_CF1017_DATA      (0x2000001a): 0x00000000_00000101
MC_CF07_DATA        (0x20000018): 0x10075012_00003400
MC_CF8F_DATA        (0x20000019): 0x18000100_287337a3
MC_CFCLK_DBUG       (0x2000001d): 0x00000000_00001000
GLCP_DELAY_CONTROLS (0x4c00000f): 0x830d415a_8ea0a36a
MC_CF_PMCTR         (0x20000020): 0x00000000_00000006
MDD_SOFT_RESET      (0x51400017): 0x00000000_00000000
MC_GLD_MSR_PM       (0x20002004): 0x00000000_00000001
GLCP_SYS_RSTPLL     (0x4c000014): 0x0000049c_07de000c

Anyway, as you've suggested, I'm sending my logs of successful
LinuxBIOS and failure coreboot-v3 startup process. I hope they will
help.

-- 
Piotr Piwko
http://www.embedded-engineering.pl/
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