[coreboot] [commit] r5147 - trunk/src/mainboard/msi/ms7135
repository service
svn at coreboot.org
Tue Feb 23 11:18:43 CET 2010
Author: oxygene
Date: Tue Feb 23 11:18:43 2010
New Revision: 5147
URL: http://tracker.coreboot.org/trac/coreboot/changeset/5147
Log:
Adjust msi/ms7135 DCACHE_RAM_* config to previous 32KiB values,
4KiB is not enough to work.
Additionally, modify the device tree so that the undocumented LDN 6
is ignored by the resource allocator, and while here, assign the
parallel port DRQ, hardware monitor IRQ and drop NIC MAC address
on SMBus EEPROM hint, the ms7135 doesn't have such hardware.
Signed-off-by: Jonathan A. Kollasch <jakllsch at kollasch.net>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>
Modified:
trunk/src/mainboard/msi/ms7135/Kconfig
trunk/src/mainboard/msi/ms7135/devicetree.cb
Modified: trunk/src/mainboard/msi/ms7135/Kconfig
==============================================================================
--- trunk/src/mainboard/msi/ms7135/Kconfig Mon Feb 22 17:41:49 2010 (r5146)
+++ trunk/src/mainboard/msi/ms7135/Kconfig Tue Feb 23 11:18:43 2010 (r5147)
@@ -109,10 +109,10 @@
config DCACHE_RAM_BASE
hex
- default 0xcf000
+ default 0xc8000
depends on BOARD_MSI_MS7135
config DCACHE_RAM_SIZE
hex
- default 0x1000
+ default 0x8000
depends on BOARD_MSI_MS7135
Modified: trunk/src/mainboard/msi/ms7135/devicetree.cb
==============================================================================
--- trunk/src/mainboard/msi/ms7135/devicetree.cb Mon Feb 22 17:41:49 2010 (r5146)
+++ trunk/src/mainboard/msi/ms7135/devicetree.cb Tue Feb 23 11:18:43 2010 (r5147)
@@ -21,6 +21,7 @@
device pnp 4e.1 on # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
+ drq 0x74 = 3
end
device pnp 4e.2 on # Com1
io 0x60 = 0x3f8
@@ -36,13 +37,14 @@
irq 0x70 = 1
irq 0x72 = 12
end
+ device pnp 4e.6 off end # XXX keep allocator happy
device pnp 4e.7 off end # Game, MIDI, GPIO 1, GPIO 5
device pnp 4e.8 off end # GPIO 2
device pnp 4e.9 off end # GPIO 3, GPIO 4
device pnp 4e.a off end # ACPI
device pnp 4e.b on # Hardware monitor
io 0x60 = 0x290
- irq 0x70 = 0
+ irq 0x70 = 5
end
end
end
@@ -64,8 +66,6 @@
register "ide1_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
- # register "mac_eeprom_smbus" = "3"
- # register "mac_eeprom_addr" = "0x51"
end
end
device pci 18.1 on end
More information about the coreboot
mailing list