[coreboot] ASUS P2B-LS support

Marc Jones marcj303 at gmail.com
Mon Feb 22 19:00:55 CET 2010

On Sun, Feb 21, 2010 at 9:49 PM, Keith Hui <buurin at gmail.com> wrote:
> Greetings.
> I just tried the CVS coreboot v2 on my Asus P2B-LS motherboard. It's also
> partially working as it is similar to the already partially supported P2B-F
> and P3B-F, which is encouraging. There are two other boards in this series,
> the P2B-L and P2B-S. They share the same circuit board with -LS and only
> omit the SCSI or LAN (respectively), so I'll concentrate my effort on LS.
> Let's begin with my results:
> CPU = OK
> L1 and L2 cache = untested
> On-board SCSI = partial (3)
> On-board LAN = untested
> PS/2 keyboard still doesn't work.
> AGP graphics card = works. Text console activated, I can see the SeaBIOS
> banner and text from the SCSI BIOS. On this run the card is a ATI 3D Rage
> IIc.
> Serial port 1 definitely works - see attached for a log
> Have not tried reboot, reset button does NOT work
> I am interested in helping completing support for this board. I have a POST
> card, a chip programmer, numerous types of PCI and AGP video cards and CPUs,
> which should cover a lot of grounds. (1) First I want to get RAM working,
> then try L2 cache, CAR if possible, keyboard/mouse, and ACPI.
> I have some x86 assembly programming experience although I have not done
> much assembly coding for years, I should still be able to understand
> datasheets.
> Before I dig right in, I want to ask what is the current state of the art
> for the P2B series.
> From what I read no one actively worked on these boards for the past couple
> years. Our boards currently need romcc, but has anyone tried doing
> cache-as-RAM on these P6 CPUs?
> Also to find out how the vendor initialized RAM, some analysis efforts were
> made on it to determine how. Will this prevent me from actually submitting a
> patch should I succeed? If so, can I instead post the how, and let some
> others code it from what I would write here?
> I was able to get a irq routing table using coreboot's own tools.
> I already made change to my working copy to add code for "slot 1 CPUs"
> (duplicated from slot 2), added P2B-LS to Kconfig with aforementioned,
> dumped, irq routing table and related code with correct "slot 1" reference.
> The log above is created after these modifications are done. I also added
> microcode updates for family 6B1 and 6B4 CPUs but it appears coreboot isn't
> catching it. I run a 6B4 Tualatin on my daily desktop. My test system
> currently has an overclocked 6B1.
> For starters, below is what I know.
> On top of what a P2B carries, P2B-LS has two extra devices:
> SCSI is on PCI 0:6.0, id 0x9005:0x001f
> LAN is on PCI 0:7.0, id 0x8086:0x1229
> In vendor BIOS the power management base port is set to 0xe400, SMBus base
> port is 0xe800
> I dumped the ACPI tables from vendor bios, haven't a chance to run it
> through iasl yet.
> I have seen code for doing ECC tests on memory (isn't a priority; I have no
> ECC memory)
> The RAM enable sequence is already very close to vendor's sequence.
> PIIX4 General purpose input #21 and #13 are used
> PIIX4 Gen Purp output #28 and #27 used
> I/O writes to port 0xe1 is used in vendor BIOS for delays
> Cheers
> Keith

Hi  Kieth,

Welcome to coreboot. It sounds like you are well on your way to
supporting this platform. I don't have any specific advice for that
board, but feel free to email the list or stop in to IRC if you have
questions. Read the developer page on the wiki and check out the
sign-off procedures. We can add this platform when you are ready to
send patches.



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