[coreboot] M57SLI is not booting successful...

Harald Gutmann harald.gutmann at gmx.net
Thu Feb 4 14:48:32 CET 2010


Just to mention it:
I tried to boot the same image now with an even number of RAM banks in the 
machine. It didn't solve anything, but it seems that the dual-channel 
detection works fine according to the log.

Here is the log with 4x1Gb in the machine:

coreboot-2.0.0-r5084M_m57sli_Fallback Thu Feb  4 12:25:04 CET 2010 starting...
*sysinfo range: [000cf000,000cf730)
bsp_apicid=00
Enabling routing table for node 00 done.
Enabling UP settings
coherent_ht_finalize
done
core0 started: 
started ap apicid:  01
SBLink=00
NC node|link=00
begin msr fid, vid 3104121204160202
Current fid_cur: 0x2, fid_max: 0x16
Requested fid_new: 0x16
FidVid table step fidvid: 0xe
FidVid table step fidvid: 0x10
FidVid table step fidvid: 0x12
FidVid table step fidvid: 0x14
200MHZ step fidvid: 0x16
end   msr fid, vid 3104120404160216
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x75
pos=0x52, unfiltered freq_cap=0x807f
pos=0x52, filtered freq_cap=0x7f
freq_cap1=0x75, freq_cap2=0x7f
dev1 old_freq=0x0, freq=0x6, needs_reset=0x1
dev2 old_freq=0x0, freq=0x6, needs_reset=0x1
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 0, reset_needed=0x1
after optimize_link_read_pointers_chain, reset_needed=0x1
mcp55_num:01
ht reset -


coreboot-2.0.0-r5084M_m57sli_Fallback Thu Feb  4 12:25:04 CET 2010 starting...
*sysinfo range: [000cf000,000cf730)
bsp_apicid=00
Enabling routing table for node 00 done.
Enabling UP settings
coherent_ht_finalize
done
core0 started: 
started ap apicid:  01
SBLink=00
NC node|link=00
begin msr fid, vid 3104120404160216
end   msr fid, vid 3104120404160216
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x75
pos=0x52, unfiltered freq_cap=0x7f
pos=0x52, filtered freq_cap=0x7f
freq_cap1=0x75, freq_cap2=0x7f
dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 0, reset_needed=0x0
after optimize_link_read_pointers_chain, reset_needed=0x0
mcp55_num:01
Ram1.00
setting up CPU 00 northbridge registers
done.
Ram2.00
sdram_set_spd_registers: paramx :000ceea8
Enabling dual channel memory
Unbuffered
400MHz
400MHz
RAM end at 0x00400000 kB
Ram3
Initializing memory:  done
RAM end at 0x00500000 kB
Setting variable MTRR 2, base:    0MB, range: 2048MB, type WB
Setting variable MTRR 3, base: 2048MB, range: 1024MB, type WB
set DQS timing:RcvrEn:Pass1: 00
 CTLRMaxDelay=1c
 done
set DQS timing:DQSPos: 00
TrainDQSRdWrPos: buf_a:000ce920
TrainDQSPos: MutualCSPassW[48] :000ce7f8
TrainDQSPos: MutualCSPassW[48] :000ce7f8
TrainDQSPos: MutualCSPassW[48] :000ce7f8
TrainDQSPos: MutualCSPassW[48] :000ce7f8
TrainDQSPos: MutualCSPassW[48] :000ce7f8
TrainDQSPos: MutualCSPassW[48] :000ce7f8
TrainDQSPos: MutualCSPassW[48] :000ce7f8
TrainDQSPos: MutualCSPassW[48] :000ce7f8
-------------- next part --------------
A non-text attachment was scrubbed...
Name: coreboot-r5084-nc-sb_4gb.log
Type: text/x-log
Size: 3208 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20100204/89119325/attachment.log>


More information about the coreboot mailing list