[coreboot] [PATCH] Intel 82830 overhaul

[Joseph Smith]

Hello,
Attached is major overhaul to the 82830 raminit. Alot of it is trivial 
clean ups. With on major change. The i830 is now able to initialize one 
row (side) of memory at a time (this is the way it is supposed to be 
done). See bootlog snip below (shows 512MB double sided SO-DIMM in 
socket 1 and 64MB single sided onboard memory) and attached patch.

Signed-off-by: Joseph Smith <joe at settoplinux.org>

coreboot-2.3" Sun Jan 31 23:42:28 EST 2010 starting...
SMBus controller enabled
Setting initial sdram registers....
Found DIMM in slot 00
DIMM is 0x0100 on side 1
DIMM is 0x0100 on side 2
DRB 0x60 has been set to 0x08
DRB1 0x61 has been set to 0x10
Found DIMM in slot 01
DIMM is 0x0040 on side 1
DIMM is 0x0000 on side 2
DRB2 0x62 has been set to 0x12
DRB3 0x63 has been set to 0x12
Found DIMM in slot 00, setting DRA...
DRA 0x70 has been set to 0x22
Found DIMM in slot 01, setting DRA...
DRA 0x71 has been set to 0xf1
Initial sdram registers have been set.
Initializing SDRAM Row 00
  NOP RAM command 0x00000010
   Sending RAM command to 0x00000000
  Pre-charging all banks RAM command 0x00000020
   Sending RAM command to 0x00000000
  8 CBR refreshes RAM command 0x00000060
   Sending RAM command to 0x00000000
RAM command 0x00000060
   Sending RAM command to 0x00000000
RAM command 0x00000060
   Sending RAM command to 0x00000000
RAM command 0x00000060
   Sending RAM command to 0x00000000
RAM command 0x00000060
   Sending RAM command to 0x00000000
RAM command 0x00000060
   Sending RAM command to 0x00000000
RAM command 0x00000060
   Sending RAM command to 0x00000000
RAM command 0x00000060
   Sending RAM command to 0x00000000
  MRS RAM command 0x00000030
   Sending RAM command to 0x000001d0
  Normal operation mode RAM command 0x00000070
   Sending RAM command to 0x00000000
  Performing dummy read/write
   Reading RAM at 0x00000000 => 0x3e5e556c
   Writing RAM at 0x00000000 <= 0x55aa55aa
   Reading RAM at 0x00000000 => 0x55aa55aa
Initializing SDRAM Row 01
  NOP RAM command 0x00000010
   Sending RAM command to 0x10000000
  Pre-charging all banks RAM command 0x00000020
   Sending RAM command to 0x10000000
  8 CBR refreshes RAM command 0x00000060
   Sending RAM command to 0x10000000
RAM command 0x00000060
   Sending RAM command to 0x10000000
RAM command 0x00000060
   Sending RAM command to 0x10000000
RAM command 0x00000060
   Sending RAM command to 0x10000000
RAM command 0x00000060
   Sending RAM command to 0x10000000
RAM command 0x00000060
   Sending RAM command to 0x10000000
RAM command 0x00000060
   Sending RAM command to 0x10000000
RAM command 0x00000060
   Sending RAM command to 0x10000000
  MRS RAM command 0x00000030
   Sending RAM command to 0x100001d0
  Normal operation mode RAM command 0x00000070
   Sending RAM command to 0x10000000
  Performing dummy read/write
   Reading RAM at 0x10000000 => 0x55abf7aa
   Writing RAM at 0x10000000 <= 0x55aa55aa
   Reading RAM at 0x10000000 => 0x55aa55aa
Initializing SDRAM Row 02
  NOP RAM command 0x00000010
   Sending RAM command to 0x20000000
  Pre-charging all banks RAM command 0x00000020
   Sending RAM command to 0x20000000
  8 CBR refreshes RAM command 0x00000060
   Sending RAM command to 0x20000000
RAM command 0x00000060
   Sending RAM command to 0x20000000
RAM command 0x00000060
   Sending RAM command to 0x20000000
RAM command 0x00000060
   Sending RAM command to 0x20000000
RAM command 0x00000060
   Sending RAM command to 0x20000000
RAM command 0x00000060
   Sending RAM command to 0x20000000
RAM command 0x00000060
   Sending RAM command to 0x20000000
RAM command 0x00000060
   Sending RAM command to 0x20000000
  MRS RAM command 0x00000030
   Sending RAM command to 0x200001d0
  Normal operation mode RAM command 0x00000070
   Sending RAM command to 0x20000000
  Performing dummy read/write
   Reading RAM at 0x20000000 => 0x55ba55aa
   Writing RAM at 0x20000000 <= 0x55aa55aa
   Reading RAM at 0x20000000 => 0x55aa55aa
Enabling Refresh
Setting initialization complete
Setting initial nothbridge registers....
Initial northbridge registers have been set.
Northbridge following SDRAM init:
PCI: 00:00.00
00: 86 80 75 35 06 00 10 00 04 00 00 06 00 00 00 00
10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
40: 09 00 05 01 00 00 00 00 00 00 00 00 02 28 00 0e
50: 72 a0 40 00 00 00 00 00 00 30 33 33 33 33 33 33
60: 08 10 12 12 12 12 00 00 00 00 00 00 00 00 00 00
70: 22 f1 ff ff 00 00 00 00 10 00 00 00 70 01 00 20
80: 00 00 00 00 00 00 00 00 80 60 33 01 00 00 00 00
90: 02 38 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 02 00 20 00 17 02 00 1f 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 54 0e 41 a2 99 01 00 c0 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 1b 49 9b fc
f0: 11 11 01 00 00 00 0b 05 35 d0 2c cf 1f cd 1d cc
Copying coreboot to RAM.
Loading stage image.
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x100000 (147456 bytes), entry @ 
0x100000
Stage: done loading.
Jumping to image.
coreboot-2.3 Sun Jan 31 23:42:28 EST 2010 booting...


-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
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