[coreboot] 440BX - DFI P2XBL - Which Target?

Kevin O'Connor kevin at koconnor.net
Thu Dec 30 21:56:13 CET 2010

On Thu, Dec 30, 2010 at 11:42:43AM -0900, Roger wrote:
> On Thu, Dec 30, 2010 at 11:09:52AM -0500, Kevin O'Connor wrote:
> >SeaBIOS runs all the option roms directly.
> I'm using the prebuilt SeaBIOS.
> I disabled the "Run VGA option ROMs" and now the lcd/vga display isn't
> initialized at all.  Guess SeaBIOS isn't executing the VGA ROM?

It tried to, but ran into an error:

> Scan for VGA option rom
> Found option rom with bad checksum: loc=0x000c0000 len=61440 sum=42

You could try compiling seabios with CONFIG_DEBUG_LEVEL set to 8.
(See http://www.coreboot.org/SeaBIOS .)

> >> Writing high table forward entry at 0x00000500
> >> Wrote coreboot table at: 00000500 - 00000518  checksum 17df
> >[...]
> >> Start bios (version 0.6.1-20100913_130029-morn.localdomain)
> >> Unable to find coreboot table!
> >> Found CBFS header at 0xfffffc9e
> >> Ram Size=0x01000000 (0x0000000000000000 high)
> >
> >Not being able to find the coreboot table is an odd error - it needs
> >to be fixed as it results in incorrect memory sizing.
> I'm searching the code and am confused what the coreboot table (ie. lb_table)
> exactly is and why it wouldn't be found.  But I'm guessing that this is
> relative to the raminit issues with the 440BX board, correct?  Especially since
> you mentioned it's an odd issue.

The coreboot table conveys critical information (like memory layout)
to the payload.  It's really odd that it gets written at 0x500 and
then lost.  Maybe you're still having memory controller issues.  If
so, you'll need to fix that before trying to fix anything else.


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