[coreboot] 440BX - DFI P2XBL - Which Target?

[Roger]

On Thu, Dec 30, 2010 at 01:55:15AM -0500, Keith Hui wrote:
>raminit is able to read SPD out of the box, so that's good news. I was
>hoping to see some differences on how it sees the RAM configuration
>between cold and warm boot, but there isn't, and it did run through
>the entire raminit. If you look at the source tree for any of those
>P2B boards, you'll see some commented out code that does a RAM test.
>You may want to enable them and see if you can access RAM. And by the
>way, all 440BX boards now use cache-as-RAM which is different from
>LinuxBIOS. Again look at those boards and see how Kconfig for such a
>board should be written up.
>
>It could also be how MBFS and MBSC was programmed. Look at the
>comments in RAM init code (I put them in) and you'll see that it only
>really applies to a 4-DIMM board. So I'll need you to do one more
>thing for me.
>Load up the factory BIOS again. Find three sticks of single sided and
>3 of double sided RAM. I'm looking for dumps of the PCI config space
>for 440BX itself, for as much combinations of RAM population you can
>collect as possible. RAM population as in which RAM stick gets
>installed in which slot. MBFS is bytes 0xCA to 0xCC. MBSC is bytes
>0x69 to 0x6E. Might as well just dump the whole 0x60 and 0xC0 rows.

Here's what I got right now.

# lspci -xxxx
00:00.0 Host bridge: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge
(rev 03)
60: 10 10 18 20 30 30 30 30 00 23 40 f7 03 e0 00 00
c0: 00 00 00 00 00 00 00 00 18 0c ff ff 7f 00 00 00

I'm going to go through my existing RAM combinations with what RAM sticks  I
have now.  I also think all of this ram is 100 and not 66.