[coreboot] question about post_cache_as_ram() function

[Patrick Georgi]

Am Freitag, 17. Dezember 2010, um 17:18:38 schrieb Fengwei Zhang:
> I checked the value from Kconfig under /mainboard/asus/m2v-mx_se/
> DCACHE_RAM_BASE is 0xcc000
> DCACHE_RAM_SIZE is 0x4000
> Why does they set to these value? Does them change?
> Do they setup by hardware?
They're mostly read out from vendor BIOS or taken from the bios developer 
manuals (which usually amounts to the same).

The values depend somewhat on the characterics of the CPU cache, so we simply 
treat them as opaque numbers for the most part.

What makes you so curious about the details of CAR setup?

> > Before that line the stack is copied from CAR to RAM, then esp is setup
> > so it points to the same place in RAM that it pointed to in CAR (that's
> > why we use sub, not mov).
> 
> i see the copying from CAR to RAM. but I still confused about the value
> of esp. Why is this euqation:
> esp = esp - (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)-
> (CONFIG_RAMTOP))
Let's define
DCACHE_TOP := DCACHE_RAM_BASE + DCACHE_RAM_SIZE
esp = DCACHE_TOP - SB with
SB := "number of bytes used on the stack" (stack grows downwards)

Then it follows that
esp' = (DCACHE_TOP - SB) - (DCACHE_TOP - RAMTOP)
= DCACHE_TOP - SB - DCACHE_TOP + RAMTOP
= DCACHE_TOP - DCACHE_TOP + RAMTOP - SB
= RAMTOP - SB

So the new stack pointer points to the same location inside the copy of the 
stack.


Patrick