[coreboot] question about post_cache_as_ram() function

Patrick Georgi patrick at georgi-clan.de
Fri Dec 17 21:29:52 CET 2010

Am Freitag, 17. Dezember 2010, um 15:08:38 schrieb Fengwei Zhang:
> I would appreciate if someone could explain a little bit for me.
DCACHE_RAM_BASE is the start address of the memory addresses that are used for 

DCACHE_RAM_SIZE is the size of that region.

RAMTOP is the highest address of the memory region that coreboot will use in 

> In addition, why do we need to set new esp here?
> 		/* set new esp */ /* before CONFIG_RAMBASE */
> 		"subl   %0, %%esp\n\t"
This moves the stack from CAR area to RAM.

While in CAR, the stack is laid out at the top end of CAR, growing downwards 
(ie. starting at DCACHE_RAM_BASE + DCACHE_RAM_SIZE).
While in RAM, it starts at the top end of the ram area used for coreboot 

Before that line the stack is copied from CAR to RAM, then esp is setup so it 
points to the same place in RAM that it pointed to in CAR (that's why we use 
sub, not mov).
This setup doesn't allow returning from the current function (we don't adjust 
addresses on the stack), but it makes sure that local variables in the scope 
of the current function are still usable.

Hope this helps,

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