[coreboot] DL145 G1 with dual dualcore CPU using coreboot ?

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Tue Aug 17 06:05:34 CEST 2010

On 16.08.2010 21:15, Myles Watson wrote:
>> The memory problem remains though. If only that can be solved, then I'm
>> basically satisfied. Any hints?
>>> Have you tried different configurations?  Coreboot is only seeing the
>>> RAM on node 0.  Where is the RAM on your board?
>> I use four 512MB DIMM's, two on each CPU, so there is one DIMM per
>> channel. The DIMM's on CPU 0 are detected but the DIMM's on CPU 1 are
>> not.
> It's possible that there is a mux in the way that needs to be set up
> correctly to allow you to read the DIMMs on the other CPU.
>> If I move all four DIMM's to CPU0 then coreboot detects 2GB but
>> hangs when initializing the memory.
> That sounds like a different problem.  Maybe the mux idea isn't right.

Very odd. Enabling DRAM debugging is a good idea.
By the way, please check if the SPDs for all DIMMs match. If the DIMMs
are just compatible and not identical, coreboot may have problems
detecting all RAM. OTOH, if all visible (from a SPD perspective) DIMMs
are also present in the computed memory count, your problem is unrelated
to what I suggested.



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