[coreboot] DL145 G1 with dual dualcore CPU using coreboot ?

Myles Watson mylesgw at gmail.com
Mon Aug 16 21:15:21 CEST 2010

> Ok I have made some progress: I finally tweaked mptable.c and
> devicetree.cb so that all peripherals work: The two ethernet NIC's, the
> Myrinet PCI-X card, IDE, USB and keyboard. Even the ILO (IPMI) card
> works fine with the ipmi driver in Linux 2.6.33.

> I don't know why lspci reports that all IRQ pins have been routed to IRQ
> 0 though (?):
I don't know where lspci gets its values.  It could be interesting to track
it down, but if it works...

> ACPI doesn't work (yet), but it just worked partially with the factory
> BIOS anyway. The SMBus and I2C devices work (they never worked with the
> factory BIOS).
> The memory problem remains though. If only that can be solved, then I'm
> basically satisfied. Any hints?
> > Have you tried different configurations?  Coreboot is only seeing the
> RAM on
> > node 0.  Where is the RAM on your board?
> >
> I use four 512MB DIMM's, two on each CPU, so there is one DIMM per
> channel. The DIMM's on CPU 0 are detected but the DIMM's on CPU 1 are
> not.
It's possible that there is a mux in the way that needs to be set up
correctly to allow you to read the DIMMs on the other CPU.

> If I move all four DIMM's to CPU0 then coreboot detects 2GB but
> hangs when initializing the memory.
That sounds like a different problem.  Maybe the mux idea isn't right.

> The same thing happens if I use two
> 1GB DIMM's.
I'd start by enabling the debugging output CONFIG_DEBUG_SMBUS.  I haven't
had to dig very much in that part of the code.


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