[coreboot] DL145 G1 with dual dualcore CPU using coreboot ?

Oskar Enoksson enok at lysator.liu.se
Mon Aug 16 20:39:50 CEST 2010


Ok I have made some progress: I finally tweaked mptable.c and
devicetree.cb so that all peripherals work: The two ethernet NIC's, the
Myrinet PCI-X card, IDE, USB and keyboard. Even the ILO (IPMI) card
works fine with the ipmi driver in Linux 2.6.33.

I don't know why lspci reports that all IRQ pins have been routed to IRQ
0 though (?):
[root at cl199 ~]# lspci -b -vvv | grep IRQ
        Interrupt: pin ? routed to IRQ 255
        Interrupt: pin D routed to IRQ 0
        Interrupt: pin A routed to IRQ 0
        Interrupt: pin A routed to IRQ 0
        Interrupt: pin B routed to IRQ 0
        Interrupt: pin D routed to IRQ 0
        Interrupt: pin D routed to IRQ 0
        Interrupt: pin A routed to IRQ 0

with the factory BIOS is looks like this:
[root at cl001 ~]# lspci -b -vvv | grep IRQ
        Interrupt: pin ? routed to IRQ 255
        Interrupt: pin D routed to IRQ 10
        Interrupt: pin D routed to IRQ 10
        Interrupt: pin A routed to IRQ 11
        Interrupt: pin A routed to IRQ 10
        Interrupt: pin B routed to IRQ 11
        Interrupt: pin A routed to IRQ 9

ACPI doesn't work (yet), but it just worked partially with the factory
BIOS anyway. The SMBus and I2C devices work (they never worked with the
factory BIOS).

The memory problem remains though. If only that can be solved, then I'm
basically satisfied. Any hints?
> Have you tried different configurations?  Coreboot is only seeing the RAM on
> node 0.  Where is the RAM on your board?
>   
I use four 512MB DIMM's, two on each CPU, so there is one DIMM per
channel. The DIMM's on CPU 0 are detected but the DIMM's on CPU 1 are
not. If I move all four DIMM's to CPU0 then coreboot detects 2GB but
hangs when initializing the memory. The same thing happens if I use two
1GB DIMM's.

Something is wrong with the way memory is detected on the second CPU,
that's for sure. This is from dmesg:

BIOS-provided physical RAM map:
 BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
 BIOS-e820: 000000000009fc00 - 00000000000a0000 (reserved)
 BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
 BIOS-e820: 0000000000100000 - 000000003ffef000 (usable)
 BIOS-e820: 000000003ffef000 - 0000000040000000 (reserved)
...
EDAC MC: Ver: 2.1.0 Aug 11 2010
EDAC amd64_edac:  Ver: 3.3.0 Aug 11 2010
EDAC amd64: ECC is enabled by BIOS.
EDAC amd64: This node reports that Memory ECC is currently disabled, set
F3x44[22] (0000:00:19.3).
EDAC amd64: ECC disabled in the BIOS or no ECC capability, module will
not load.
 Either enable ECC checking or force module loading by setting
'ecc_enable_override'.
 (Note that use of the override may cause unknown side effects.)
amd64_edac: probe of 0000:00:19.2 failed with error -22
EDAC MC: Rev E or earlier detected
EDAC MC0: Giving out device to 'amd64_edac' 'RevF': DEV 0000:00:18.2
EDAC PCI0: Giving out device to module 'amd64_edac' controller 'EDAC PCI
controller': DEV '0000:00:18.2' (POLLED)


The output from "svn diff src/mainboard" is in attachment 1
The console output "SPEW" level from coreboot is in attachment 2

Thanks.

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