[coreboot] DL145 G1 with dual dualcore CPU using coreboot ?

[Oskar Enoksson]

Myles Watson wrote:
> On Mon, Aug 9, 2010 at 8:16 AM, Myles Watson <mylesgw at gmail.com> wrote:
>   
>> On Sat, Aug 7, 2010 at 9:57 AM, Oskar Enoksson <enok at lysator.liu.se> wrote:
>>     
>>> Ok, I'm able to hotswap the BIOS chip, burn it and hot-remove it without
>>> stopping the "development server" , then moving it to the target server
>>> and power it up (although it takes some effort to avoid bending the pins)
>>>       
>> Great.
>>
>>     
>>> However I'm not getting any output whatsoever from the target server.
>>> Nothing on the serial port, nothing on the VGA output.
>>>       
>> Have you tested the serial port under Linux?  I'm surprised that you
>> don't see anything since the board is so similar.
>>     
>
> I wouldn't even copy the directory until you see serial output.  If
> you've tested the serial port under Linux, then I would build coreboot
> images for boards with the same chipsets & SuperIO until you find one
> that gives you some output.
>
> Thanks,
> Myles
>   
I'm finally getting output now. The problem was that this server has a
IPMI board (HP calls it "ILO Integrated Lights Out  management").
Somehow the server's hardware serial port is initially redirected to
this management board and not to the RS232 port. By connecting to the
management board through the dedicated IPMI ethernet port and using
telnet I'm able to see the output that coreboot believes it's writing to
the RS232 port.

... and after trying a few different motherboard configurations I got
success: an image built from the Tyan S2881 image boots. Even the VGA
screen wakes up in the end, displaying the last output from coreboot.
Here is the end of the output:

coreboot memory table:
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000c0000-000000003ffeffff: RAM
 3. 000000003fff0000-000000003fffffff: CONFIGURATION TABLES
Wrote coreboot table at: 3fffe000 - 3fffe1a8  checksum 5169
coreboot table: 424 bytes.
POST: 0x9e
 0. FREE SPACE 40000000 00000000
 1. GDT        3fff0200 00000200
 2. IRQ TABLE  3fff0400 00001000
 3. SMP TABLE  3fff1400 00001000
 4. ACPI       3fff2400 0000bc00
 5. COREBOOT   3fffe000 00002000
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff80000 + 38 + cb8a + align -> fff8cc00
Check
CBFS: follow chain: fff8cc00 + 28 + 633b8 + align -> ffff0000
CBFS:  Could not find file fallback/payload
Boot failed.