[coreboot] What is the rule of the SPD address assignment if there are more that 8 dimm slots?

[Marc Jones]

2010/7/31 Stefan Reinauer <stefan.reinauer at coresystems.de>:
> On 7/31/10 4:56 PM, Zheng Bao wrote:
>
> The board tht I am working on has 2 process. Each of them has 6 DIMM slots.
> If you
> plug 1 dimm into each slot, the SPD address will be,
>   Channel  PCB
>   ----------------
> P0:
>   DIMMA0   50h
>   DIMMA1   51h
>   DIMMA2   52h
>   DIMMB0   53h
>   DIMMB1   54h
>   DIMMB2   55h
> P1:
>   DIMMA0   50h
>   DIMMA1   51h
>   DIMMA2   52h
>   DIMMB0   53h
>   DIMMB1   54h
>   DIMMB2   55h
> If you plug 1 dimm in P0DIMMA0 and the other in P1DIMA0, the SPD address
> will be 50h and 55h.
> So I am confused. If we got an active spd 0x50 on the SMBUS, what will it
> be?
> It seems that we can not plug more that 8 dimm even if we have 12 slots,
> correct?
>
> Zheng
>
>
>
> There is probably an smbus hub for switching between the P0 and P1 SPD ROMs.
>
> Check out src/mainboard/tyan/s4880/romstage.c for an example of a board with
> smbus hub.

Another example is in the serengeti_cheetah romstage.c activate_spd_rom().


Marc


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