[coreboot] [commit] r5471 - in trunk/src: cpu/amd/model_gx2 cpu/amd/model_lx devices/oprom include/cpu/amd mainboard/amd/db800 mainboard/amd/norwich mainboard/artecgroup/dbe61 mainboard/digitallogic/msm800sev...
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svn at coreboot.org
Wed Apr 21 22:06:11 CEST 2010
Author: stepan
Date: Wed Apr 21 22:06:10 2010
New Revision: 5471
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5471
Log:
* clean up all but two warnings on artecgroup dbe61
* integrate vsm init into normal x86.c code (so it can run above 1M)
* call void main(unsigned long bist) except void cache_as_ram_main(void)
on Geode LX (as we do on almost all other platforms now)
* Unify Geode LX MSR setup (will bring most non-working LX targets back
to life)
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>
Added:
trunk/src/cpu/amd/model_lx/msrinit.c
Deleted:
trunk/src/cpu/amd/model_gx2/vsmsetup.c
trunk/src/cpu/amd/model_lx/vsmsetup.c
Modified:
trunk/src/cpu/amd/model_gx2/Kconfig
trunk/src/cpu/amd/model_gx2/Makefile.inc
trunk/src/cpu/amd/model_lx/Kconfig
trunk/src/cpu/amd/model_lx/Makefile.inc
trunk/src/cpu/amd/model_lx/cache_as_ram.inc
trunk/src/devices/oprom/x86.c
trunk/src/devices/oprom/x86_asm.S
trunk/src/include/cpu/amd/lxdef.h
trunk/src/mainboard/amd/db800/romstage.c
trunk/src/mainboard/amd/norwich/romstage.c
trunk/src/mainboard/artecgroup/dbe61/Kconfig
trunk/src/mainboard/artecgroup/dbe61/romstage.c
trunk/src/mainboard/digitallogic/msm800sev/romstage.c
trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
trunk/src/mainboard/lippert/roadrunner-lx/romstage.c
trunk/src/mainboard/lippert/spacerunner-lx/romstage.c
trunk/src/mainboard/pcengines/alix1c/romstage.c
trunk/src/mainboard/winent/pl6064/romstage.c
trunk/src/northbridge/amd/gx2/Kconfig
trunk/src/northbridge/amd/lx/Kconfig
trunk/src/northbridge/amd/lx/northbridge.c
trunk/src/southbridge/amd/cs5536/cs5536.h
trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c
Modified: trunk/src/cpu/amd/model_gx2/Kconfig
==============================================================================
--- trunk/src/cpu/amd/model_gx2/Kconfig Wed Apr 21 08:36:20 2010 (r5470)
+++ trunk/src/cpu/amd/model_gx2/Kconfig Wed Apr 21 22:06:10 2010 (r5471)
@@ -42,7 +42,7 @@
config VSA_FILE
string "AMD Geode GX2 VSA path and filename"
- depends on GEODE_VSA
+ depends on GEODE_VSA && CPU_AMD_GX2
default "gpl_vsa_gx_102.bin"
help
The path and filename of the file to use as VSA.
Modified: trunk/src/cpu/amd/model_gx2/Makefile.inc
==============================================================================
--- trunk/src/cpu/amd/model_gx2/Makefile.inc Wed Apr 21 08:36:20 2010 (r5470)
+++ trunk/src/cpu/amd/model_gx2/Makefile.inc Wed Apr 21 22:06:10 2010 (r5471)
@@ -4,4 +4,3 @@
subdirs-y += ../../x86/smm
driver-y += model_gx2_init.o
obj-y += cpubug.o
-obj-y += vsmsetup.o
Modified: trunk/src/cpu/amd/model_lx/Kconfig
==============================================================================
--- trunk/src/cpu/amd/model_lx/Kconfig Wed Apr 21 08:36:20 2010 (r5470)
+++ trunk/src/cpu/amd/model_lx/Kconfig Wed Apr 21 22:06:10 2010 (r5471)
@@ -23,7 +23,7 @@
config VSA_FILE
string "AMD Geode LX VSA path and filename"
- depends on GEODE_VSA
+ depends on GEODE_VSA && CPU_AMD_LX
default "gpl_vsa_lx_102.bin"
help
The path and filename of the file to use as VSA.
Modified: trunk/src/cpu/amd/model_lx/Makefile.inc
==============================================================================
--- trunk/src/cpu/amd/model_lx/Makefile.inc Wed Apr 21 08:36:20 2010 (r5470)
+++ trunk/src/cpu/amd/model_lx/Makefile.inc Wed Apr 21 22:06:10 2010 (r5471)
@@ -5,6 +5,5 @@
driver-y += model_lx_init.o
obj-y += cpubug.o
-obj-y += vsmsetup.o
cpu_incs += $(src)/cpu/amd/model_lx/cache_as_ram.inc
Modified: trunk/src/cpu/amd/model_lx/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/amd/model_lx/cache_as_ram.inc Wed Apr 21 08:36:20 2010 (r5470)
+++ trunk/src/cpu/amd/model_lx/cache_as_ram.inc Wed Apr 21 22:06:10 2010 (r5471)
@@ -34,6 +34,8 @@
/**
/***************************************************************************/
DCacheSetup:
+ /* Save the BIST result */
+ movl %eax, %ebx
invd
/* set cache properties */
@@ -173,9 +175,17 @@
hlt /* issues */
jmp DCacheSetupBad
DCacheSetupGood:
-
/* Go do early init and memory setup */
- call cache_as_ram_main
+
+ /* Restore the BIST result */
+ movl %ebx, %eax
+ movl %esp, %ebp
+ pushl %eax
+
+ post_code(0x23)
+
+ /* Call romstage.c main function */
+ call main
done_cache_as_ram_main:
/* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */
Added: trunk/src/cpu/amd/model_lx/msrinit.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ trunk/src/cpu/amd/model_lx/msrinit.c Wed Apr 21 22:06:10 2010 (r5471)
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+struct msrinit {
+ u32 msrnum;
+ msr_t msr;
+};
+
+static const struct msrinit msr_table[] =
+{
+ {CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB.
+ * Rom Properties: Write Serialize, WriteProtect.
+ * RomBase: 0xFFFC0
+ * SysTop to RomBase Properties: Write Serialize, Cache Disable.
+ * SysTop: 0x000A0
+ * System Memory Properties: (Write Back) */
+ {CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */
+ {CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */
+ {CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */
+
+ /* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */
+ {MSR_GLIU0_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
+ {MSR_GLIU0_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
+ {MSR_GLIU0_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
+ {MSR_GLIU1_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
+ {MSR_GLIU1_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
+ {MSR_GLIU1_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
+};
+
+static void msr_init(void)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(msr_table); i++)
+ wrmsr(msr_table[i].msrnum, msr_table[i].msr);
+}
+
+
Modified: trunk/src/devices/oprom/x86.c
==============================================================================
--- trunk/src/devices/oprom/x86.c Wed Apr 21 08:36:20 2010 (r5470)
+++ trunk/src/devices/oprom/x86.c Wed Apr 21 22:06:10 2010 (r5471)
@@ -1,7 +1,8 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2009-2010 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -36,9 +37,11 @@
extern unsigned char __idt_handler, __idt_handler_size;
extern unsigned char __realmode_code, __realmode_code_size;
extern unsigned char __run_optionrom, __run_interrupt;
+extern unsigned char __run_vsa;
void (*run_optionrom)(u32 devfn) __attribute__((regparm(0))) = (void *)&__run_optionrom;
void (*vga_enable_console)(void) __attribute__((regparm(0))) = (void *)&__run_interrupt;
+void (*run_vsa)(u32 smm, u32 sysmem) __attribute__((regparm(0))) = (void *)&__run_vsa;
int (*intXX_handler[256])(struct eregs *regs) = { NULL };
@@ -160,6 +163,88 @@
printk(BIOS_DEBUG, "... Option ROM returned.\n");
}
+#if defined(CONFIG_GEODE_VSA) && CONFIG_GEODE_VSA
+#include <cpu/amd/lxdef.h>
+#include <cpu/amd/vr.h>
+#include <cbfs.h>
+
+#define VSA2_BUFFER 0x60000
+#define VSA2_ENTRY_POINT 0x60020
+
+// TODO move to a header file.
+void do_vsmbios(void);
+
+/* VSA virtual register helper */
+static u32 VSA_vrRead(u16 classIndex)
+{
+ u32 eax, ebx, ecx, edx;
+ asm volatile (
+ "movw $0x0AC1C, %%dx\n"
+ "orl $0x0FC530000, %%eax\n"
+ "outl %%eax, %%dx\n"
+ "addb $2, %%dl\n"
+ "inw %%dx, %%ax\n"
+ : "=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx)
+ : "a"(classIndex)
+ );
+
+ return eax;
+}
+
+void do_vsmbios(void)
+{
+ printk(BIOS_DEBUG, "Preparing for VSA...\n");
+
+ /* clear bios data area */
+ memset((void *)0x400, 0, 0x200);
+
+ /* Set up C interrupt handlers */
+ setup_interrupt_handlers();
+
+ /* Setting up realmode IDT */
+ setup_realmode_idt();
+
+ memcpy(REALMODE_BASE, &__realmode_code, (size_t)&__realmode_code_size);
+ printk(BIOS_SPEW, "VSA: Real mode stub @%p: %d bytes\n", REALMODE_BASE,
+ (u32)&__realmode_code_size);
+
+ if ((unsigned int)cbfs_load_stage("vsa") != VSA2_ENTRY_POINT) {
+ printk(BIOS_ERR, "Failed to load VSA.\n");
+ return;
+ }
+
+ unsigned char *buf = (unsigned char *)VSA2_BUFFER;
+ printk(BIOS_DEBUG, "VSA: Buffer @%p *[0k]=%02x\n", buf, buf[0]);
+ printk(BIOS_DEBUG, "VSA: Signature *[0x20-0x23] is %02x:%02x:%02x:%02x\n",
+ buf[0x20], buf[0x21], buf[0x22], buf[0x23]);
+
+ /* Check for code to emit POST code at start of VSA. */
+ if ((buf[0x20] != 0xb0) || (buf[0x21] != 0x10) ||
+ (buf[0x22] != 0xe6) || (buf[0x23] != 0x80)) {
+ printk(BIOS_WARNING, "VSA: Signature incorrect. Install failed.\n");
+ return;
+ }
+
+ printk(BIOS_DEBUG, "Calling VSA module...\n");
+ /* ECX gets SMM, EDX gets SYSMEM */
+ run_vsa(MSR_GLIU0_SMM, MSR_GLIU0_SYSMEM);
+ printk(BIOS_DEBUG, "... VSA module returned.\n");
+
+ /* Restart timer 1 */
+ outb(0x56, 0x43);
+ outb(0x12, 0x41);
+
+ /* Check that VSA is running OK */
+ if (VSA_vrRead(SIGNATURE) == VSA2_SIGNATURE)
+ printk(BIOS_DEBUG, "VSM: VSA2 VR signature verified.\n");
+ else
+ printk(BIOS_ERR, "VSM: VSA2 VR signature not valid. Install failed.\n");
+}
+#endif
+
+/* interrupt_handler() is called from assembler code only,
+ * so there is no use in putting the prototype into a header file.
+ */
int __attribute__((regparm(0))) interrupt_handler(u32 intnumber,
u32 gsfs, u32 dses,
u32 edi, u32 esi,
Modified: trunk/src/devices/oprom/x86_asm.S
==============================================================================
--- trunk/src/devices/oprom/x86_asm.S Wed Apr 21 08:36:20 2010 (r5470)
+++ trunk/src/devices/oprom/x86_asm.S Wed Apr 21 22:06:10 2010 (r5471)
@@ -155,6 +155,105 @@
popal
ret
+#if defined(CONFIG_GEODE_VSA) && CONFIG_GEODE_VSA
+#define VSA2_ENTRY_POINT 0x60020
+
+ .globl __run_vsa
+__run_vsa = RELOCATED(.)
+ /* save all registers to the stack */
+ pushal
+
+ /* Move the protected mode stack to a safe place */
+ mov %esp, __stack
+
+ movl %esp, %ebp
+ /* This function is called with regparm=0 and we have
+ * to skip the 32 byte from pushal:
+ */
+ movl 36(%ebp), %ecx
+ movl 40(%ebp), %edx
+
+ /* Activate the right segment descriptor real mode. */
+ ljmp $0x28, $RELOCATED(1f)
+1:
+.code16
+ /* 16 bit code from here on... */
+
+ /* Load the segment registers w/ properly configured
+ * segment descriptors. They will retain these
+ * configurations (limits, writability, etc.) once
+ * protected mode is turned off.
+ */
+ mov $0x30, %ax
+ mov %ax, %ds
+ mov %ax, %es
+ mov %ax, %fs
+ mov %ax, %gs
+ mov %ax, %ss
+
+ /* Turn off protection */
+ movl %cr0, %eax
+ andl $~PE, %eax
+ movl %eax, %cr0
+
+ /* Now really going into real mode */
+ ljmp $0, $RELOCATED(1f)
+1:
+ /* Setup a stack: Put the stack at the end of page zero.
+ * That way we can easily share it between real and
+ * protected, since the 16-bit ESP at segment 0 will
+ * work for any case. */
+ mov $0x0, %ax
+ mov %ax, %ss
+ movl $0x1000, %eax
+ movl %eax, %esp
+
+ /* Load our 16 bit idt */
+ xor %ax, %ax
+ mov %ax, %ds
+ lidt __realmode_idt
+
+ /* Set all segments to 0x0000, ds to 0x0040 */
+ mov %ax, %es
+ mov %ax, %fs
+ mov %ax, %gs
+ mov $0x40, %ax
+ mov %ax, %ds
+ mov %cx, %ax // restore ax
+
+ /* ************************************ */
+ lcall $((VSA2_ENTRY_POINT & 0xffff0000) >> 4), $(VSA2_ENTRY_POINT & 0xffff)
+ /* ************************************ */
+
+ /* If we got here, just about done.
+ * Need to get back to protected mode
+ */
+ movl %cr0, %eax
+ orl $PE, %eax
+ movl %eax, %cr0
+
+ /* Now that we are in protected mode
+ * jump to a 32 bit code segment.
+ */
+ data32 ljmp $0x10, $RELOCATED(1f)
+1:
+ .code32
+ movw $0x18, %ax
+ mov %ax, %ds
+ mov %ax, %es
+ mov %ax, %fs
+ mov %ax, %gs
+ mov %ax, %ss
+
+ /* restore proper idt */
+ lidt idtarg
+
+ /* and exit */
+ mov __stack, %esp
+ popal
+ ret
+#endif
+
.globl __run_interrupt
__run_interrupt = RELOCATED(.)
Modified: trunk/src/include/cpu/amd/lxdef.h
==============================================================================
--- trunk/src/include/cpu/amd/lxdef.h Wed Apr 21 08:36:20 2010 (r5470)
+++ trunk/src/include/cpu/amd/lxdef.h Wed Apr 21 22:06:10 2010 (r5471)
@@ -623,6 +623,12 @@
#define SMM_OFFSET 0x80400000 /* above 2GB */
#define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */
-
+#if !defined(__ROMCC__) && !defined(ASSEMBLY)
+#if defined(__PRE_RAM__)
+void cpuRegInit(void);
+void SystemPreInit(void);
+#endif
+void cpubug(void);
+#endif
#endif
Modified: trunk/src/mainboard/amd/db800/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/db800/romstage.c Wed Apr 21 08:36:20 2010 (r5470)
+++ trunk/src/mainboard/amd/db800/romstage.c Wed Apr 21 22:06:10 2010 (r5471)
@@ -57,46 +57,14 @@
#include "lib/generic_sdram.c"
#include "cpu/amd/model_lx/cpureginit.c"
#include "cpu/amd/model_lx/syspreinit.c"
-
-struct msrinit {
- u32 msrnum;
- msr_t msr;
- };
-
-static const struct msrinit msr_table[] =
-{
- {CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB.
- * Rom Properties: Write Serialize, WriteProtect.
- * RomBase: 0xFFFC0
- * SysTop to RomBase Properties: Write Serialize, Cache Disable.
- * SysTop: 0x000A0
- * System Memory Properties: (Write Back) */
- {CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */
- {CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */
- {CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */
-
- /* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */
- {MSR_GLIU0_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
- {MSR_GLIU0_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
- {MSR_GLIU0_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
- {MSR_GLIU1_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
- {MSR_GLIU1_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
- {MSR_GLIU1_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
-};
-
-static void msr_init(void)
-{
- int i;
- for (i = 0; i < ARRAY_SIZE(msr_table); i++)
- wrmsr(msr_table[i].msrnum, msr_table[i].msr);
-}
+#include "cpu/amd/model_lx/msrinit.c"
static void mb_gpio_init(void)
{
/* Early mainboard specific GPIO setup. */
}
-void cache_as_ram_main(void)
+void main(unsigned long bist)
{
post_code(0x01);
@@ -117,6 +85,9 @@
uart_init();
console_init();
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
pll_reset(ManualConf);
cpuRegInit();
Modified: trunk/src/mainboard/amd/norwich/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/norwich/romstage.c Wed Apr 21 08:36:20 2010 (r5470)
+++ trunk/src/mainboard/amd/norwich/romstage.c Wed Apr 21 22:06:10 2010 (r5471)
@@ -52,46 +52,14 @@
#include "lib/generic_sdram.c"
#include "cpu/amd/model_lx/cpureginit.c"
#include "cpu/amd/model_lx/syspreinit.c"
-
-static void msr_init(void)
-{
- msr_t msr;
-
- /* Setup access to the cache for under 1MB. */
- msr.hi = 0x24fffc02;
- msr.lo = 0x1000A000; /* 0-A0000 write back */
- wrmsr(CPU_RCONF_DEFAULT, msr);
-
- msr.hi = 0x0; /* write back */
- msr.lo = 0x0;
- wrmsr(CPU_RCONF_A0_BF, msr);
- wrmsr(CPU_RCONF_C0_DF, msr);
- wrmsr(CPU_RCONF_E0_FF, msr);
-
- /* Setup access to the cache for under 640K. Note MC not setup yet. */
- msr.hi = 0x20000000;
- msr.lo = 0xfff80;
- wrmsr(MSR_GLIU0 + 0x20, msr);
-
- msr.hi = 0x20000000;
- msr.lo = 0x80fffe0;
- wrmsr(MSR_GLIU0 + 0x21, msr);
-
- msr.hi = 0x20000000;
- msr.lo = 0xfff80;
- wrmsr(MSR_GLIU1 + 0x20, msr);
-
- msr.hi = 0x20000000;
- msr.lo = 0x80fffe0;
- wrmsr(MSR_GLIU1 + 0x21, msr);
-}
+#include "cpu/amd/model_lx/msrinit.c"
static void mb_gpio_init(void)
{
/* Early mainboard specific GPIO setup. */
}
-void cache_as_ram_main(void)
+void main(unsigned long bist)
{
post_code(0x01);
@@ -116,6 +84,9 @@
uart_init();
console_init();
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
pll_reset(ManualConf);
cpuRegInit();
Modified: trunk/src/mainboard/artecgroup/dbe61/Kconfig
==============================================================================
--- trunk/src/mainboard/artecgroup/dbe61/Kconfig Wed Apr 21 08:36:20 2010 (r5470)
+++ trunk/src/mainboard/artecgroup/dbe61/Kconfig Wed Apr 21 22:06:10 2010 (r5471)
@@ -31,7 +31,7 @@
default 3
depends on BOARD_ARTECGROUP_DBE61
-config RAMBASE
- hex
- default 0x4000
- depends on BOARD_ARTECGROUP_DBE61
+#config RAMBASE
+# hex
+# default 0x4000
+## depends on BOARD_ARTECGROUP_DBE61
Modified: trunk/src/mainboard/artecgroup/dbe61/romstage.c
==============================================================================
--- trunk/src/mainboard/artecgroup/dbe61/romstage.c Wed Apr 21 08:36:20 2010 (r5470)
+++ trunk/src/mainboard/artecgroup/dbe61/romstage.c Wed Apr 21 22:06:10 2010 (r5471)
@@ -45,9 +45,9 @@
{
int i;
- if (device == DIMM0){
- for (i=0; i < (ARRAY_SIZE(spd_table)); i++){
- if (spd_table[i].address == address){
+ if (device == DIMM0) {
+ for (i=0; i < (ARRAY_SIZE(spd_table)); i++) {
+ if (spd_table[i].address == address) {
return spd_table[i].data;
}
}
@@ -69,46 +69,14 @@
#include "lib/generic_sdram.c"
#include "cpu/amd/model_lx/cpureginit.c"
#include "cpu/amd/model_lx/syspreinit.c"
-
-struct msrinit {
- u32 msrnum;
- msr_t msr;
-};
-
-static const struct msrinit msr_table[] =
-{
- {CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB.
- * Rom Properties: Write Serialize, WriteProtect.
- * RomBase: 0xFFFC0
- * SysTop to RomBase Properties: Write Serialize, Cache Disable.
- * SysTop: 0x000A0
- * System Memory Properties: (Write Back) */
- {CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */
- {CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */
- {CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */
-
- /* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */
- {MSR_GLIU0_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
- {MSR_GLIU0_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
- {MSR_GLIU0_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
- {MSR_GLIU1_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
- {MSR_GLIU1_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
- {MSR_GLIU1_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
-};
-
-static void msr_init(void)
-{
- int i;
- for (i = 0; i < ARRAY_SIZE(msr_table); i++)
- wrmsr(msr_table[i].msrnum, msr_table[i].msr);
-}
+#include "cpu/amd/model_lx/msrinit.c"
static void mb_gpio_init(void)
{
/* Early mainboard specific GPIO setup */
}
-void cache_as_ram_main(void)
+void main(unsigned long bist)
{
post_code(0x01);
@@ -137,6 +105,9 @@
uart_init();
console_init();
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
pll_reset(ManualConf);
cpuRegInit();
@@ -144,8 +115,7 @@
sdram_initialize(1, memctrl);
/* Dump memory configuratation */
- /*{
- msr_t msr;
+#if 0
msr = rdmsr(MC_CF07_DATA);
print_debug("MC_CF07_DATA: ");
print_debug_hex32(MC_CF07_DATA);
@@ -173,9 +143,10 @@
print_debug_hex32(msr.lo);
msr = rdmsr(MC_CF8F_DATA);
print_debug(" \n");
- }*/
+#endif
/* Check memory. */
- /* ram_check(0x00000000, 640 * 1024); */
+ // ram_check(0x00000000, 640 * 1024);
+ // ram_check(1024 * 1024, 2 * 1024 * 1024);
}
Modified: trunk/src/mainboard/digitallogic/msm800sev/romstage.c
==============================================================================
--- trunk/src/mainboard/digitallogic/msm800sev/romstage.c Wed Apr 21 08:36:20 2010 (r5470)
+++ trunk/src/mainboard/digitallogic/msm800sev/romstage.c Wed Apr 21 22:06:10 2010 (r5471)
@@ -35,30 +35,14 @@
#include "lib/generic_sdram.c"
#include "cpu/amd/model_lx/cpureginit.c"
#include "cpu/amd/model_lx/syspreinit.c"
-
-static void msr_init(void)
-{
- msr_t msr;
- /* Setup access to the MC for under 1MB. Note MC not setup yet. */
- msr.hi = 0x24fffc02;
- msr.lo = 0x10010000;
- wrmsr(CPU_RCONF_DEFAULT, msr);
-
- msr.hi = 0x20000000;
- msr.lo = 0xfff00;
- wrmsr(MSR_GLIU0 + 0x20, msr);
-
- msr.hi = 0x20000000;
- msr.lo = 0xfff00;
- wrmsr(MSR_GLIU1 + 0x20, msr);
-}
+#include "cpu/amd/model_lx/msrinit.c"
static void mb_gpio_init(void)
{
/* Early mainboard specific GPIO setup */
}
-void cache_as_ram_main(void)
+void main(unsigned long bist)
{
post_code(0x01);
@@ -81,6 +65,9 @@
uart_init();
console_init();
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
pll_reset(ManualConf);
cpuRegInit();
Modified: trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Wed Apr 21 08:36:20 2010 (r5470)
+++ trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Wed Apr 21 22:06:10 2010 (r5471)
@@ -60,46 +60,14 @@
#include "lib/generic_sdram.c"
#include "cpu/amd/model_lx/cpureginit.c"
#include "cpu/amd/model_lx/syspreinit.c"
-
-static void msr_init(void)
-{
- msr_t msr;
-
- /* Setup access to the cache for under 1MB. */
- msr.hi = 0x24fffc02;
- msr.lo = 0x1000A000; /* 0-A0000 write back */
- wrmsr(CPU_RCONF_DEFAULT, msr);
-
- msr.hi = 0x0; /* Write back */
- msr.lo = 0x0;
- wrmsr(CPU_RCONF_A0_BF, msr);
- wrmsr(CPU_RCONF_C0_DF, msr);
- wrmsr(CPU_RCONF_E0_FF, msr);
-
- /* Setup access to the cache for under 640K. Note MC not setup yet. */
- msr.hi = 0x20000000;
- msr.lo = 0xfff80;
- wrmsr(MSR_GLIU0 + 0x20, msr);
-
- msr.hi = 0x20000000;
- msr.lo = 0x80fffe0;
- wrmsr(MSR_GLIU0 + 0x21, msr);
-
- msr.hi = 0x20000000;
- msr.lo = 0xfff80;
- wrmsr(MSR_GLIU1 + 0x20, msr);
-
- msr.hi = 0x20000000;
- msr.lo = 0x80fffe0;
- wrmsr(MSR_GLIU1 + 0x21, msr);
-}
+#include "cpu/amd/model_lx/msrinit.c"
static void mb_gpio_init(void)
{
/* Early mainboard specific GPIO setup. */
}
-void cache_as_ram_main(void)
+void main(unsigned long bist)
{
post_code(0x01);
@@ -120,6 +88,9 @@
uart_init();
console_init();
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
pll_reset(ManualConf);
cpuRegInit();
Modified: trunk/src/mainboard/lippert/roadrunner-lx/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Wed Apr 21 08:36:20 2010 (r5470)
+++ trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Wed Apr 21 22:06:10 2010 (r5471)
@@ -60,39 +60,7 @@
#include "lib/generic_sdram.c"
#include "cpu/amd/model_lx/cpureginit.c"
#include "cpu/amd/model_lx/syspreinit.c"
-
-static void msr_init(void)
-{
- msr_t msr;
-
- /* Setup access to the cache for under 1MB. */
- msr.hi = 0x24fffc02;
- msr.lo = 0x1000A000; /* 0-A0000 write back */
- wrmsr(CPU_RCONF_DEFAULT, msr);
-
- msr.hi = 0x0; /* Write back */
- msr.lo = 0x0;
- wrmsr(CPU_RCONF_A0_BF, msr);
- wrmsr(CPU_RCONF_C0_DF, msr);
- wrmsr(CPU_RCONF_E0_FF, msr);
-
- /* Setup access to the cache for under 640K. Note MC not setup yet. */
- msr.hi = 0x20000000;
- msr.lo = 0xfff80;
- wrmsr(MSR_GLIU0 + 0x20, msr);
-
- msr.hi = 0x20000000;
- msr.lo = 0x80fffe0;
- wrmsr(MSR_GLIU0 + 0x21, msr);
-
- msr.hi = 0x20000000;
- msr.lo = 0xfff80;
- wrmsr(MSR_GLIU1 + 0x20, msr);
-
- msr.hi = 0x20000000;
- msr.lo = 0x80fffe0;
- wrmsr(MSR_GLIU1 + 0x21, msr);
-}
+#include "cpu/amd/model_lx/msrinit.c"
static const u16 sio_init_table[] = { // hi=data, lo=index
0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...)
@@ -128,7 +96,7 @@
it8712f_exit_conf();
}
-void cache_as_ram_main(void)
+void main(unsigned long bist)
{
post_code(0x01);
@@ -150,6 +118,9 @@
uart_init();
console_init();
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
pll_reset(ManualConf);
cpuRegInit();
Modified: trunk/src/mainboard/lippert/spacerunner-lx/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Wed Apr 21 08:36:20 2010 (r5470)
+++ trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Wed Apr 21 22:06:10 2010 (r5471)
@@ -122,39 +122,7 @@
#include "lib/generic_sdram.c"
#include "cpu/amd/model_lx/cpureginit.c"
#include "cpu/amd/model_lx/syspreinit.c"
-
-static void msr_init(void)
-{
- msr_t msr;
-
- /* Setup access to the cache for under 1MB. */
- msr.hi = 0x24fffc02;
- msr.lo = 0x1000A000; /* 0-A0000 write back */
- wrmsr(CPU_RCONF_DEFAULT, msr);
-
- msr.hi = 0x0; /* Write back */
- msr.lo = 0x0;
- wrmsr(CPU_RCONF_A0_BF, msr);
- wrmsr(CPU_RCONF_C0_DF, msr);
- wrmsr(CPU_RCONF_E0_FF, msr);
-
- /* Setup access to the cache for under 640K. Note MC not setup yet. */
- msr.hi = 0x20000000;
- msr.lo = 0xfff80;
- wrmsr(MSR_GLIU0 + 0x20, msr);
-
- msr.hi = 0x20000000;
- msr.lo = 0x80fffe0;
- wrmsr(MSR_GLIU0 + 0x21, msr);
-
- msr.hi = 0x20000000;
- msr.lo = 0xfff80;
- wrmsr(MSR_GLIU1 + 0x20, msr);
-
- msr.hi = 0x20000000;
- msr.lo = 0x80fffe0;
- wrmsr(MSR_GLIU1 + 0x21, msr);
-}
+#include "cpu/amd/model_lx/msrinit.c"
static const u16 sio_init_table[] = { // hi=data, lo=index
0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...)
@@ -189,7 +157,7 @@
it8712f_exit_conf();
}
-void cache_as_ram_main(void)
+void main(unsigned long bist)
{
int err;
post_code(0x01);
@@ -212,6 +180,9 @@
uart_init();
console_init();
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
pll_reset(ManualConf);
cpuRegInit();
Modified: trunk/src/mainboard/pcengines/alix1c/romstage.c
==============================================================================
--- trunk/src/mainboard/pcengines/alix1c/romstage.c Wed Apr 21 08:36:20 2010 (r5470)
+++ trunk/src/mainboard/pcengines/alix1c/romstage.c Wed Apr 21 22:06:10 2010 (r5471)
@@ -115,31 +115,14 @@
#include "lib/generic_sdram.c"
#include "cpu/amd/model_lx/cpureginit.c"
#include "cpu/amd/model_lx/syspreinit.c"
-
-static void msr_init(void)
-{
- msr_t msr;
-
- /* Setup access to the MC for under 1MB. Note MC not setup yet. */
- msr.hi = 0x24fffc02;
- msr.lo = 0x10010000;
- wrmsr(CPU_RCONF_DEFAULT, msr);
-
- msr.hi = 0x20000000;
- msr.lo = 0xfff00;
- wrmsr(MSR_GLIU0 + 0x20, msr);
-
- msr.hi = 0x20000000;
- msr.lo = 0xfff00;
- wrmsr(MSR_GLIU1 + 0x20, msr);
-}
+#include "cpu/amd/model_lx/msrinit.c"
/** Early mainboard specific GPIO setup. */
static void mb_gpio_init(void)
{
}
-void cache_as_ram_main(void)
+void main(unsigned long bist)
{
static const struct mem_controller memctrl[] = {
{.channel0 = {0x50}},
@@ -161,6 +144,9 @@
uart_init();
console_init();
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
pll_reset(ManualConf);
cpuRegInit();
Modified: trunk/src/mainboard/winent/pl6064/romstage.c
==============================================================================
--- trunk/src/mainboard/winent/pl6064/romstage.c Wed Apr 21 08:36:20 2010 (r5470)
+++ trunk/src/mainboard/winent/pl6064/romstage.c Wed Apr 21 22:06:10 2010 (r5471)
@@ -57,46 +57,14 @@
#include "lib/generic_sdram.c"
#include "cpu/amd/model_lx/cpureginit.c"
#include "cpu/amd/model_lx/syspreinit.c"
-
-struct msrinit {
- u32 msrnum;
- msr_t msr;
- };
-
-static const struct msrinit msr_table[] =
-{
- {CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB.
- * Rom Properties: Write Serialize, WriteProtect.
- * RomBase: 0xFFFC0
- * SysTop to RomBase Properties: Write Serialize, Cache Disable.
- * SysTop: 0x000A0
- * System Memory Properties: (Write Back) */
- {CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */
- {CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */
- {CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */
-
- /* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */
- {MSR_GLIU0_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
- {MSR_GLIU0_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
- {MSR_GLIU0_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
- {MSR_GLIU1_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
- {MSR_GLIU1_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
- {MSR_GLIU1_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
-};
-
-static void msr_init(void)
-{
- int i;
- for (i = 0; i < ARRAY_SIZE(msr_table); i++)
- wrmsr(msr_table[i].msrnum, msr_table[i].msr);
-}
+#include "cpu/amd/model_lx/msrinit.c"
static void mb_gpio_init(void)
{
/* Early mainboard specific GPIO setup. */
}
-void cache_as_ram_main(void)
+void main(unsigned long bist)
{
post_code(0x01);
@@ -118,6 +86,9 @@
uart_init();
console_init();
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
pll_reset(ManualConf);
cpuRegInit();
Modified: trunk/src/northbridge/amd/gx2/Kconfig
==============================================================================
--- trunk/src/northbridge/amd/gx2/Kconfig Wed Apr 21 08:36:20 2010 (r5470)
+++ trunk/src/northbridge/amd/gx2/Kconfig Wed Apr 21 22:06:10 2010 (r5471)
@@ -19,4 +19,6 @@
config NORTHBRIDGE_AMD_GX2
bool
+ # for VSM:
+ select PCI_OPTION_ROM_RUN_REALMODE
Modified: trunk/src/northbridge/amd/lx/Kconfig
==============================================================================
--- trunk/src/northbridge/amd/lx/Kconfig Wed Apr 21 08:36:20 2010 (r5470)
+++ trunk/src/northbridge/amd/lx/Kconfig Wed Apr 21 22:06:10 2010 (r5471)
@@ -1,6 +1,8 @@
config NORTHBRIDGE_AMD_LX
bool
select HAVE_HIGH_TABLES
+ # for VSM:
+ select PCI_OPTION_ROM_RUN_REALMODE
config VIDEO_MB
int
Modified: trunk/src/northbridge/amd/lx/northbridge.c
==============================================================================
--- trunk/src/northbridge/amd/lx/northbridge.c Wed Apr 21 08:36:20 2010 (r5470)
+++ trunk/src/northbridge/amd/lx/northbridge.c Wed Apr 21 22:06:10 2010 (r5471)
@@ -74,11 +74,8 @@
#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}}
#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}}
-extern void graphics_init(void);
-extern void cpubug(void);
-extern void chipsetinit(void);
-
-void setup_realmode_idt(void);
+void print_conf(void);
+void graphics_init(void);
void do_vsmbios(void);
struct msr_defaults {
@@ -319,7 +316,7 @@
//printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo);
}
-void northbridge_set_resources(struct device *dev)
+static void northbridge_set_resources(struct device *dev)
{
struct resource *resource, *last;
unsigned link;
@@ -426,7 +423,6 @@
static void pci_domain_enable(device_t dev)
{
-
printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
// do this here for now -- this chip really breaks our device model
@@ -434,14 +430,10 @@
cpubug();
chipsetinit();
- setup_realmode_idt();
-
- printk(BIOS_DEBUG, "Before VSA:\n");
// print_conf();
do_vsmbios(); // do the magic stuff here, so prepare your tambourine ;)
- printk(BIOS_DEBUG, "After VSA:\n");
// print_conf();
graphics_init();
Modified: trunk/src/southbridge/amd/cs5536/cs5536.h
==============================================================================
--- trunk/src/southbridge/amd/cs5536/cs5536.h Wed Apr 21 08:36:20 2010 (r5470)
+++ trunk/src/southbridge/amd/cs5536/cs5536.h Wed Apr 21 22:06:10 2010 (r5471)
@@ -464,4 +464,13 @@
#define FLASH_IO_128B 0x0000FF80
#define FLASH_IO_256B 0x0000FF00
+#if !defined(ASSEMBLY) && !defined(__ROMCC__)
+#if defined(__PRE_RAM__)
+void cs5536_setup_onchipuart(int uart);
+void cs5536_disable_internal_uart(void);
+#else
+void chipsetinit(void);
+#endif
+#endif
+
#endif /* _CS5536_H */
Modified: trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c
==============================================================================
--- trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c Wed Apr 21 08:36:20 2010 (r5470)
+++ trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c Wed Apr 21 22:06:10 2010 (r5471)
@@ -121,7 +121,7 @@
outl(val, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
}
-static void cs5536_disable_internal_uart(void)
+void cs5536_disable_internal_uart(void)
{
msr_t msr;
/* The UARTs default to enabled.
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