[coreboot] EP80579 reference platform

[Dustin Harrison]

On Thu, Apr 15, 2010 at 2:04 PM, Dustin Harrison
>>> Question:  I thought I read somewhere the ROMCC is no longer used?  
>>> Is that
>>> true for the entire project?  Because I see that ROMCC is still used 
>>> for
>>> romstage.c
>>
>> I don't know the status of romcc, but it wouldn't be a shock to
>> discover that a bug has crept into romcc, or the Truxton mainboard
>> code, or the i3100 southbridge code.
>>
>> I'd recommend you try building a revision of Coreboot from around the
>> time I committed the Truxton code
>> (http://tracker.coreboot.org/trac/coreboot/changeset/3656/trunk).
>>
> Good suggestion - So I've built coreboot-v2 and I can now get to the 
> "Jumping to coreboot" line.  Looking at older posts it appears that 
> Arnaud had to play with some RAM settings to get past this issue, so 
> I'll start there.
>
> Tomorrow I'll have a look at the difference between the assembly code 
> generated and see if there is anything obvious.
>
I tried to compare the assembly output in coreboot-v2 rev3656 and 
coreboot rev:trunk.  r3656 gets as far as jumping to coreboot and hangs 
which I have determined is due to my RAM settings.  However, after 
applying the patch Ed sent me, coreboot trunk hangs at the 
"dump_spd_registers" line 280 in mainboard/intel/jarrell/debug.c:

279:        print_debug("dimm ");
280:        print_debug_hex8(device);

Doing a visual diff of auto.inc and romstange.inc I can see that the 
while loop that the above lines are contained within compiled to 
assembly differently between the two versions, however I went back to 
svn rev 4051 of romcc and built trunk and this made no difference.  So 
it seems the problem lies somewhere in the include files.

I need to focus on my ram settings right now so I can at least move 
forward with rev3656, but if anyone has some ideas I'll give them a shot 
in between hacking the RAM.

Cheers
Dustin