[coreboot] [commit] r5462 - trunk/src/northbridge/intel/i945
repository service
svn at coreboot.org
Tue Apr 20 17:52:58 CEST 2010
Author: oxygene
Date: Tue Apr 20 17:52:57 2010
New Revision: 5462
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5462
Log:
Make RAM init on i945GC work
Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi at coresystems.de>
Modified:
trunk/src/northbridge/intel/i945/raminit.c
Modified: trunk/src/northbridge/intel/i945/raminit.c
==============================================================================
--- trunk/src/northbridge/intel/i945/raminit.c Tue Apr 20 17:49:59 2010 (r5461)
+++ trunk/src/northbridge/intel/i945/raminit.c Tue Apr 20 17:52:57 2010 (r5462)
@@ -2048,10 +2048,6 @@
{
u32 clkcfg;
u8 reg8;
- u8 offset = 0;
-#ifdef CHIPSET_I945GM
- offset++;
-#endif
printk(BIOS_DEBUG, "Setting Memory Frequency... ");
@@ -2073,9 +2069,9 @@
}
switch (sysinfo->memory_frequency) {
- case 400: clkcfg |= ((1+offset) << 4); break;
- case 533: clkcfg |= ((2+offset) << 4); break;
- case 667: clkcfg |= ((3+offset) << 4); break;
+ case 400: clkcfg |= (2 << 4); break;
+ case 533: clkcfg |= (3 << 4); break;
+ case 667: clkcfg |= (4 << 4); break;
default: die("Target Memory Frequency Error");
}
@@ -2187,7 +2183,7 @@
0x10080201, 0x00000000, /* DDR400 FSB533 */
0x00100401, 0x00000000, /* DDR533 FSB533 */
- 0xffffffff, 0xffffffff, /* nonexistant */
+ 0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistant */
@@ -2209,7 +2205,7 @@
0x00010800, 0x00000402, /* DDR400 FSB533 */
0x01000400, 0x00000200, /* DDR533 FSB533 */
- 0xffffffff, 0xffffffff, /* nonexistant */
+ 0x00020904, 0x00000000, /* DDR667 FSB533 - fake values */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistant */
More information about the coreboot
mailing list