[coreboot] (no subject)

[Stefan Reinauer]

On 4/19/10 11:34 PM, Uwe Hermann wrote:
> On Mon, Apr 12, 2010 at 06:32:16AM +0200, Marc Bertens wrote:
>   
>> Signed-off-by: Marc Bertens <mbertens at xs4all.nl>
>>     
> Thanks, committed in r5458 with some of the changes I mentioned.
> Sorry for the delay.
>
> Can you please post lspci -tvnn and some more status info? I'd like
> to add a wiki page for the board, similar to this one:
>
> http://www.coreboot.org/ASUS_P2B
>   

Just reading that page... it says level 2 cache is not enabled...
However, the cpu driver (model_6xx_init.c) says:

static void model_6xx_init(device_t dev)
{
        /* Turn on caching if we haven't already */
        x86_enable_cache();
        x86_setup_mtrrs(36);
        x86_mtrr_check();

        /* Update the microcode */
        intel_update_microcode(microcode_updates);

        /* Enable the local cpu apics */
        setup_lapic();
};


So it should be enough to add your CPU to the cpu_table in order to get
L2 cache enabled.


Stefan