[coreboot] EP80579 reference platform

[Dustin Harrison]

On 13/04/2010 11:56 PM, Stefan Reinauer wrote:
> On 4/14/10 4:18 AM, Dustin Harrison wrote:
>
>> I've put several print_info statements in romstage.c and narrowed it 
>> down to the following line in i3100_early_lpc.c:
>>
>> pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1 << 7));
>>
>> Further debug shows that in general I can not read a value and then 
>> use the value.  If I just perfrom a read operation it executes the 
>> instruction and contiues.  But if I do a read and try to use a 
>> print_info_hexXX function it just hangs.
>
> Can you try this patch please?
>
Hi Stefan,

I applied your patch and was able to reproduce the same results as 
before -- I can move past the TCO initialization, but then I get stuck 
the next time a variable is referenced.  In the EP80579 case that is 
spd_dump_registers:

void dump_spd_registers(void)
{
         unsigned device;
         device = SMBUS_MEM_DEVICE_START;
         while(device <= SMBUS_MEM_DEVICE_END) {
                 int status = 0;
                 int i;
                 print_debug("\n");
                 print_debug("dimm ");
                 print_debug_hex8(device);

The print_debug_hex8(device) hangs now.  I can re-create this behaviour 
simply be doing any sort of read or variable assignment and then try to 
use a print_XXX function on the data.  For example if I change the above 
function to the following:

Index: src/mainboard/intel/jarrell/debug.c
===================================================================
--- src/mainboard/intel/jarrell/debug.c (revision 5430)
+++ src/mainboard/intel/jarrell/debug.c (working copy)
@@ -275,12 +275,9 @@
          while(device <= SMBUS_MEM_DEVICE_END) {
                  int status = 0;
                  int i;
-               print_debug("\n");
-                print_debug("dimm ");
-               print_debug_hex8(device);

                  for(i = 0; (i < 256) ; i++) {
-                       unsigned char byte;
+                        print_debug("here now.\n");
                          if ((i % 16) == 0) {
                                 print_debug("\n");
                                 print_debug_hex8(i);


I now get stuck on the for loop (I never see "here now").
I have switched to using the coreboot toolchain and it doesn't seem to 
make a difference.

These are the last few lines of assembly before the jump to the 
print_debug_hex8(i) section:

ffff0aaf:       66 0f 6e c7             movd   %edi,%xmm0
ffff0ab3:       bc 00 00 00 00          mov    $0x0,%esp
ffff0ab8:       e9 a8 05 00 00          jmp    ffff1065 <L1496>
ffff1065 <L1496>:
ffff1065:       66 0f 7e c7             movd   %xmm0,%edi
ffff1069:       81 fc 00 01 00 00       cmp    $0x100,%esp
ffff106f:       0f 8c 48 fa ff ff       jl     ffff0abd <L1368>
ffff0abd <L1368>:  /* At this point we are working on 
print_debug_hex8(i) now */
ffff0abd:       bd 6a d0 ff ff          mov    $0xffffd06a,%ebp

I am also in the process of trying my BIOS in the truxton platform, but 
it will take me a while to get things up and going.  In the meantime I'm 
out of ideas on how to narrow this down any further.

Cheers
Dustin



> Index: src/southbridge/intel/i3100/i3100_early_lpc.c
> ===================================================================
> --- src/southbridge/intel/i3100/i3100_early_lpc.c    (revision 5413)
> +++ src/southbridge/intel/i3100/i3100_early_lpc.c    (working copy)
> @@ -34,13 +34,14 @@
>  {
>      device_t dev = PCI_DEV(0x0, 0x1f, 0x0);
>
> -    /* Temporarily enable the ACPI I/O range at 0x4000 */
> -    pci_write_config32(dev, 0x40, 0x4000 | (1 << 0));
> -    pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1 
> << 7));
> +#define ABASE 0x400
> +    /* Temporarily enable the ACPI I/O range at ABASE */
> +    pci_write_config32(dev, 0x40, ABASE | (1 << 0));
> +    pci_write_config8(dev, 0x44, (1 << 7));
>
>      /* Halt the TCO timer, preventing SMI and automatic reboot */
> -    outw(inw(0x4068) | (1 << 11), 0x4068);
> +    outw(inw(ABASE + 0x68) | (1 << 11), ABASE + 0x68);
>
>      /* Disable the ACPI I/O range */
> -    pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) & ~(1 
> << 7));
> +    pci_write_config8(dev, 0x44, 0);
>  }
>
>
>>
>> Any ideas on what to try next?  Is there a recommended toolchain?
> Yes, you can compile it with
> $ cd coreboot/util/crossgcc
> $ sh buildgcc
>
> coreboot will automatically pick it up. You might have to delete 
> coreboot/.xcompile in order to have coreboot pick it up.
>
> Stefan
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