[coreboot] unstable AMD Fam10h boot
stepan at coresystems.de
Tue Sep 8 19:29:10 CEST 2009
Peter Stuge wrote:
> Stefan Reinauer wrote:
>>> RAM init working concurrently with multiple memory controllers -
>>> they're on PCI, right?
>> But why would it not be completely sufficient to set up all ram
>> controllers in the system from the BSP?
> The big coreboot SMP win is with ECC scrubbing, right?
Yes, but that does not happen until we're in stage2. It's not really
part of memory init.
> Does that
> involve some PCI config space accesses to the memory controllers?
I don't think so.
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