[coreboot] unstable AMD Fam10h boot

Stefan Reinauer stepan at coresystems.de
Sun Sep 6 21:40:06 CEST 2009

Peter Stuge wrote:
> Stefan Reinauer wrote:
>> Since there is only one set of PCI devices, I wonder what the
>> benefit would be to "penetrate" them from all CPU cores or what
>> would even cause that as a requirement.
> RAM init working concurrently with multiple memory controllers -
> they're on PCI, right?

But why would it not be completely sufficient to set up all ram
controllers in the system from the BSP?

Or, put differently.

We're smart and we fix the PCI problem. Then we suddenly notice that
that is not enough. because a PCI operation is by no means an atomic
operation. We're going to have to add another layer of locking on top of
that, for example for SMBUS access, which might involve PCI access.

I'm saying we're opening a can of worms here, and unless we really like
to go fishing we should close it again and walk in the dry.


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