[coreboot] unstable AMD Fam10h boot
stepan at coresystems.de
Sat Sep 5 19:36:02 CEST 2009
ron minnich wrote:
> So, what I'm trying to say:
> - we have a problem on fam10h
> - it seems to be a non-smp-safe function doing a config cycle
> - there are two ways to eliminate the problem
> o write a fam10 version of that function that will use MMCONF (will
> work on all later CPUs)
> o modify old function by adding a lock (i.e. stick with legacy
> mechanism for older CPUs)
Another idea would be to get rid of SMP setup in CAR stage. It sounds
highly funky to me anyways.
- Why are we doing this anyways?
o Is there a reason?
o No other SMP system except K10 does this.
* How many ms do we benefit from that? (Honest question). Any at all?
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