[coreboot] unstable AMD Fam10h boot
rminnich at gmail.com
Fri Sep 4 19:06:21 CEST 2009
On Fri, Sep 4, 2009 at 9:57 AM, Myles Watson<mylesgw at gmail.com> wrote:
>> > As ports CF8/CFC are shared across cores (maybe even sockets?)
>> > accesses from different cores may yield random results.
>> I would be surprised were they shared across sockets but ...
>> I'm realizing I have no clue how config cycles work on Opteron. I just
>> assumed this cf8/cfc cycle was magically converted inside the cpu into
>> an HT cycle of some sort, and that cycle was routed via the config
>> space maps in the NB. But ... can someone inform me on how this really
>> works? Is my picture even close?
> I don't know how the conversion works exactly, or where it takes place, but
> the HT packet is a read or a write to 0xFD.FE00.0000 + an offset for the
> UnitID(pci device number). So, for device 7 on the bus and config register
> 0x14, you get 0xFDFE003814. You don't have to worry about bus numbers
> because they get taken care of based on the HT chain the to which the packet
> is routed.
This is a memory read/write?
> Based on that, I would say it's not shared across sockets, but it definitely
> could be shared across cores.
> Isn't there a way to do MMCONF cycles from the NB?
Marc? If there were, it would make sense to convert the code to use
these, instead of trying to make cf8/cfc SMP-safe.
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