[coreboot] unstable AMD Fam10h boot

Myles Watson mylesgw at gmail.com
Fri Sep 4 18:57:02 CEST 2009

> > As ports CF8/CFC are shared across cores (maybe even sockets?)
> concurrent
> > accesses from different cores may yield random results.
> I would be surprised were they shared across sockets but ...
> I'm realizing I have no clue how config cycles work on Opteron. I just
> assumed this cf8/cfc cycle was magically converted inside the cpu into
> an HT cycle of some sort, and that cycle was routed via the config
> space maps in the NB. But ... can someone inform me on how this really
> works? Is my picture even close?

I don't know how the conversion works exactly, or where it takes place, but
the HT packet is a read or a write to 0xFD.FE00.0000 + an offset for the
UnitID(pci device number).  So, for device 7 on the bus and config register
0x14, you get 0xFDFE003814.  You don't have to worry about bus numbers
because they get taken care of based on the HT chain the to which the packet
is routed.

Based on that, I would say it's not shared across sockets, but it definitely
could be shared across cores.

> Is there some better way on fam10 to do config cycles that is more
> multi-core friendly? It seems odd that we are still locked into this
> cf8/cfc stuff.
Isn't there a way to do MMCONF cycles from the NB?


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