[coreboot] unstable AMD Fam10h boot

ron minnich rminnich at gmail.com
Fri Sep 4 18:29:07 CEST 2009

On Tue, Sep 1, 2009 at 2:15 PM, Ralf Grosse Boerger<ralfgb at gmail.com> wrote:
> Hi,
> this a reply to the following message:
> http://www.coreboot.org/pipermail/coreboot/2009-August/051629.html
> [I am not subscribed to this list.]
> The sporadic boot problems ("FIXME! CPU Version unknown or not supported!")
> are caused by a race condition in Get_NB32().
> This function performs a read operation to the PCI configuration space via
> port CF8/CFC.
> u32 Get_NB32(u32 dev, u32 reg)
> {
>        u32 addr;
>        addr = (dev>>4) | (reg & 0xFF) | ((reg & 0xf00)<<16);
>        outl((1<<31) | (addr & ~3), 0xcf8);
>        return inl(0xcfc);
> }
> As ports CF8/CFC are shared across cores (maybe even sockets?) concurrent
> accesses from different cores may yield random results.

I would be surprised were they shared across sockets but ...
I'm realizing I have no clue how config cycles work on Opteron. I just
assumed this cf8/cfc cycle was magically converted inside the cpu into
an HT cycle of some sort, and that cycle was routed via the config
space maps in the NB. But ... can someone inform me on how this really
works? Is my picture even close?

Is there some better way on fam10 to do config cycles that is more
multi-core friendly? It seems odd that we are still locked into this
cf8/cfc stuff.


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