[coreboot] unstable AMD Fam10h boot

Ralf Grosse Boerger ralfgb at gmail.com
Tue Sep 1 23:15:34 CEST 2009


this a reply to the following message:
[I am not subscribed to this list.]

The sporadic boot problems ("FIXME! CPU Version unknown or not  
supported!") are caused by a race condition in Get_NB32().

This function performs a read operation to the PCI configuration space via  
port CF8/CFC.

u32 Get_NB32(u32 dev, u32 reg)
	u32 addr;

	addr = (dev>>4) | (reg & 0xFF) | ((reg & 0xf00)<<16);
	outl((1<<31) | (addr & ~3), 0xcf8);

	return inl(0xcfc);

As ports CF8/CFC are shared across cores (maybe even sockets?) concurrent  
accesses from different cores may yield random results.

This race condition is not limited to mctGetLogicalCPUID(), but should  
affect any PCI configuration space access.
A real bugfix requires some sort of mutex, but mutexes are difficult to  
implement (this was already discusses on this list).

If the cores are started sequentially, concurrent PCI accesses can be  
I'll post example code as soon as I find some time...

Best Regards

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