[coreboot] FW: [PATCH]: vga bios was added into image by cbfstool, not by "cat" any more.
Stefan Reinauer
stepan at coresystems.de
Thu Oct 29 10:03:39 CET 2009
Bao, Zheng wrote:
> Ping. Have you guys tested on all the supported boards?
>
> Zheng
>
Untested, but the patch looks look. You shouldn't need
CONFIG_VGA_ROM_RUN on boards with CONFIG_PCI_ROM_RUN set already.
CONFIG_PCI_ROM_RUN: Run all option roms
CONFIG_VGA_ROM_RUN: Run only VGA option roms
Stefan
>
>
> -----Original Message-----
> From: coreboot-bounces at coreboot.org
> [mailto:coreboot-bounces at coreboot.org] On Behalf Of Bao, Zheng
> Sent: Friday, October 16, 2009 4:20 PM
> To: Carl-Daniel Hailfinger
> Cc: coreboot at coreboot.org
> Subject: Re: [coreboot] [PATCH]: vga bios was added into image by
> cbfstool,not by "cat" any more.
>
> Other board has been fixed. Please have a test.
>
> Add CONFIG_VGA_ROM_RUN to tim5690, tim8690, kt690, otherwise the
> VGA ROM can not run. After make, run
>
>> ./cbfs/cbfstool ./coreboot.rom add ../vga_bios.rom pci1002,791f.rom
>>
> optionrom
> to make the final image with vga bios.
>
> The macro vga_rom_address is out-of-date when CBFS starts play its role.
> it also should
> be eliminated from rs690/chip.h.
>
> Zheng
>
> Signed-off-by: Zheng Bao <zheng.bao at amd.com>
>
>
>
>
> Index: src/southbridge/amd/rs690/chip.h
> ===================================================================
> --- src/southbridge/amd/rs690/chip.h (revision 4782)
> +++ src/southbridge/amd/rs690/chip.h (working copy)
> @@ -23,7 +23,6 @@
> /* Member variables are defined in Config.lb. */
> struct southbridge_amd_rs690_config
> {
> - u32 vga_rom_address; /* The location that the VGA rom
> has been appened. */
> u8 gpp_configuration; /* The configuration of General Purpose
> Port, A/B/C/D/E. */
> u8 port_enable; /* Which port is enabled? GFX(2,3),
> GPP(4,5,6,7) */
> u8 gfx_dev2_dev3; /* for GFX Core initialization
> REFCLK_SEL */
> Index: src/mainboard/kontron/kt690/Options.lb
> ===================================================================
> --- src/mainboard/kontron/kt690/Options.lb (revision 4782)
> +++ src/mainboard/kontron/kt690/Options.lb (working copy)
> @@ -91,6 +91,7 @@
> uses CONFIG_VIDEO_MB
> uses CONFIG_GFXUMA
> uses CONFIG_HAVE_MAINBOARD_RESOURCES
> +uses CONFIG_VGA_ROM_RUN
>
> ###
> ### Build options
> @@ -161,6 +162,7 @@
> #VGA Console
> default CONFIG_CONSOLE_VGA=1
> default CONFIG_PCI_ROM_RUN=1
> +default CONFIG_VGA_ROM_RUN=1
>
> # BTDC: Only one HT device on Herring.
> #HT Unit ID offset
> Index: src/mainboard/kontron/kt690/Config.lb
> ===================================================================
> --- src/mainboard/kontron/kt690/Config.lb (revision 4782)
> +++ src/mainboard/kontron/kt690/Config.lb (working copy)
> @@ -136,7 +136,6 @@
> #The variables belong to mainboard are defined here.
>
> #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
> -#Define vga_rom_address = 0xfff0000
> #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
> #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or
> Dev3,
> # 1: the system allows a PCIE
> link to be established on Dev2 or Dev3.
> @@ -170,7 +169,6 @@
> device pci 6.0 on end # PCIE P2P
> bridge 0x7916
> device pci 7.0 on end # PCIE P2P
> bridge 0x7917
> device pci 8.0 off end # NB/SB
> Link P2P bridge
> - register "vga_rom_address" =
> "0xfff00000"
> register "gpp_configuration" =
> "4"
> register "port_enable" = "0xfc"
> register "gfx_dev2_dev3" = "1"
> Index: src/mainboard/kontron/kt690/devicetree.cb
> ===================================================================
> --- src/mainboard/kontron/kt690/devicetree.cb (revision 4782)
> +++ src/mainboard/kontron/kt690/devicetree.cb (working copy)
> @@ -1,5 +1,4 @@
> #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
> -#Define vga_rom_address = 0xfff0000
> #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
> #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or
> Dev3,
> # 1: the system allows a PCIE
> link to be established on Dev2 or Dev3.
> @@ -33,7 +32,6 @@
> device pci 6.0 on end # PCIE P2P
> bridge 0x7916
> device pci 7.0 on end # PCIE P2P
> bridge 0x7917
> device pci 8.0 off end # NB/SB
> Link P2P bridge
> - register "vga_rom_address" =
> "0xfff00000"
> register "gpp_configuration" =
> "4"
> register "port_enable" = "0xfc"
> register "gfx_dev2_dev3" = "1"
> Index: src/mainboard/technexion/tim8690/Options.lb
> ===================================================================
> --- src/mainboard/technexion/tim8690/Options.lb (revision 4782)
> +++ src/mainboard/technexion/tim8690/Options.lb (working copy)
> @@ -90,6 +90,7 @@
> uses CONFIG_VIDEO_MB
> uses CONFIG_GFXUMA
> uses CONFIG_HAVE_MAINBOARD_RESOURCES
> +uses CONFIG_VGA_ROM_RUN
>
> ###
> ### Build options
> @@ -159,6 +160,7 @@
> #VGA Console
> default CONFIG_CONSOLE_VGA=1
> default CONFIG_PCI_ROM_RUN=1
> +default CONFIG_VGA_ROM_RUN=1
>
> # BTDC: Only one HT device on Herring.
> #HT Unit ID offset
> Index: src/mainboard/technexion/tim8690/Config.lb
> ===================================================================
> --- src/mainboard/technexion/tim8690/Config.lb (revision 4782)
> +++ src/mainboard/technexion/tim8690/Config.lb (working copy)
> @@ -136,7 +136,6 @@
> #The variables belong to mainboard are defined here.
>
> #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
> -#Define vga_rom_address = 0xfff80000
> #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
> #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or
> Dev3,
> # 1: the system allows a PCIE
> link to be established on Dev2 or Dev3.
> @@ -170,7 +169,6 @@
> device pci 6.0 on end # PCIE P2P
> bridge 0x7916
> device pci 7.0 on end # PCIE P2P
> bridge 0x7917
> device pci 8.0 off end # NB/SB
> Link P2P bridge
> - register "vga_rom_address" =
> "0xfff80000"
> register "gpp_configuration" =
> "4"
> register "port_enable" = "0xfc"
> register "gfx_dev2_dev3" = "1"
> Index: src/mainboard/technexion/tim8690/devicetree.cb
> ===================================================================
> --- src/mainboard/technexion/tim8690/devicetree.cb (revision 4782)
> +++ src/mainboard/technexion/tim8690/devicetree.cb (working copy)
> @@ -1,5 +1,4 @@
> #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
> -#Define vga_rom_address = 0xfff80000
> #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
> #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or
> Dev3,
> # 1: the system allows a PCIE link to be
> established on Dev2 or Dev3.
> @@ -33,7 +32,6 @@
> device pci 6.0 on end # PCIE P2P
> bridge 0x7916
> device pci 7.0 on end # PCIE P2P
> bridge 0x7917
> device pci 8.0 off end # NB/SB
> Link P2P bridge
> - register "vga_rom_address" =
> "0xfff80000"
> register "gpp_configuration" =
> "4"
> register "port_enable" = "0xfc"
> register "gfx_dev2_dev3" = "1"
> Index: src/mainboard/technexion/tim5690/Config.lb
> ===================================================================
> --- src/mainboard/technexion/tim5690/Config.lb (revision 4782)
> +++ src/mainboard/technexion/tim5690/Config.lb (working copy)
> @@ -136,7 +136,6 @@
> #The variables belong to mainboard are defined here.
>
> #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
> -#Define vga_rom_address = 0xfff80000
> #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
> #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or
> Dev3,
> # 1: the system allows a PCIE link to be
> established on Dev2 or Dev3.
> @@ -173,10 +172,6 @@
> device pci 6.0 on end # PCIE P2P
> bridge 0x7916
> device pci 7.0 on end # PCIE P2P
> bridge 0x7917
> device pci 8.0 off end # NB/SB
> Link P2P bridge
> - register "vga_rom_address" =
> "0xfff80000"
> - #register "vga_rom_address" =
> "0xfff00000"
> - #register "vga_rom_address" =
> "0xffe00000"
> - #register "vga_rom_address" =
> "0xffc00000"
> register "gpp_configuration" =
> "4"
> register "port_enable" = "0xfc"
> register "gfx_dev2_dev3" = "1"
> Index: src/mainboard/technexion/tim5690/devicetree.cb
> ===================================================================
> --- src/mainboard/technexion/tim5690/devicetree.cb (revision 4782)
> +++ src/mainboard/technexion/tim5690/devicetree.cb (working copy)
> @@ -1,5 +1,4 @@
> #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
> -#Define vga_rom_address = 0xfff80000
> #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
> #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or
> Dev3,
> # 1: the system allows a PCIE link to be
> established on Dev2 or Dev3.
> @@ -36,10 +35,6 @@
> device pci 6.0 on end # PCIE P2P
> bridge 0x7916
> device pci 7.0 on end # PCIE P2P
> bridge 0x7917
> device pci 8.0 off end # NB/SB
> Link P2P bridge
> - register "vga_rom_address" =
> "0xfff80000"
> - #register "vga_rom_address" =
> "0xfff00000"
> - #register "vga_rom_address" =
> "0xffe00000"
> - #register "vga_rom_address" =
> "0xffc00000"
> register "gpp_configuration" =
> "4"
> register "port_enable" = "0xfc"
> register "gfx_dev2_dev3" = "1"
> Index: targets/kontron/kt690/Config.lb
> ===================================================================
> --- targets/kontron/kt690/Config.lb (revision 4783)
> +++ targets/kontron/kt690/Config.lb (working copy)
> @@ -4,14 +4,14 @@
> mainboard kontron/kt690
>
> romimage "normal"
> - option CONFIG_ROM_SIZE = 1024*1024 - 55808
> + option CONFIG_ROM_SIZE = 1024*1024
> option CONFIG_USE_FALLBACK_IMAGE=0
> option CONFIG_ROM_IMAGE_SIZE=0x20000
> option CONFIG_XIP_ROM_SIZE=0x20000
> payload ../payload.elf
> end
>
> -romimage "fallback"
> +romimage "fallback"
> option CONFIG_USE_FALLBACK_IMAGE=1
> option CONFIG_ROM_IMAGE_SIZE=0x20000
> option CONFIG_XIP_ROM_SIZE=0x20000
> Index: targets/technexion/tim8690/Config.lb
> ===================================================================
> --- targets/technexion/tim8690/Config.lb (revision 4783)
> +++ targets/technexion/tim8690/Config.lb (working copy)
> @@ -3,17 +3,16 @@
> target tim8690
> mainboard technexion/tim8690
>
> -
> romimage "normal"
> - option CONFIG_ROM_SIZE = 1024*512 - 55808
> + option CONFIG_ROM_SIZE = 1024*512
> option CONFIG_USE_FALLBACK_IMAGE=0
> option CONFIG_ROM_IMAGE_SIZE=0x20000
> option CONFIG_XIP_ROM_SIZE=0x20000
> payload /home/daniel/mypayloads/link
> end
>
> -romimage "fallback"
> - option CONFIG_FALLBACK_SIZE= 1024*512 - 55808
> +romimage "fallback"
> + option CONFIG_FALLBACK_SIZE= 1024*512
> option CONFIG_USE_FALLBACK_IMAGE=1
> option CONFIG_ROM_IMAGE_SIZE=0x20000
> option CONFIG_XIP_ROM_SIZE=0x20000
> @@ -21,7 +20,7 @@
>
> end
>
> -buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
> +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
>
>
>
> Index: targets/technexion/tim5690/Config.lb
> ===================================================================
> --- targets/technexion/tim5690/Config.lb (revision 4783)
> +++ targets/technexion/tim5690/Config.lb (working copy)
> @@ -19,7 +19,7 @@
> payload ../payload.elf
> end
>
> -romimage "fallback"
> +romimage "fallback"
> option CONFIG_USE_FALLBACK_IMAGE=1
> option CONFIG_ROM_IMAGE_SIZE=0x20000
> option CONFIG_XIP_ROM_SIZE=0x20000
> @@ -27,5 +27,5 @@
> payload ../payload.elf
> end
>
> -buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
> +buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
>
>
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