[coreboot] [sassmann at redhat.com: boot interrupts - the next step]
peter at stuge.se
Mon Oct 19 19:04:11 CEST 2009
This from linux-kernel today.
I'm glad to see this forward thinking. :)
----- Forwarded message from Stefan Assmann <sassmann at redhat.com> -----
From: Stefan Assmann <sassmann at redhat.com>
To: Linux Kernel Mailing List <linux-kernel at vger.kernel.org>
CC: linux-acpi at vger.kernel.org, andi at firstfloor.org,
Arjan van de Ven <arjan at infradead.org>, Ingo Molnar <mingo at elte.hu>,
Jon Masters <jcm at redhat.com>, Len Brown <lenb at kernel.org>,
tokunaga.keiich at jp.fujitsu.com, Olaf Dabrunz <Olaf.Dabrunz at gmx.net>,
greg at kroah.com
Subject: boot interrupts - the next step
Date: Mon, 19 Oct 2009 12:31:15 +0200
boot interrupts are a major pain for linux interrupt handling. I'm not
going into detail here, explaining it all over again. In case you want to
know more refer to the links below.
While we're still fighting this chipset generations boot interrupts
there's something we can do to prevent next gens chipsets from generating
Therefore we need support from BIOS people. In fact ACPI has a method
to "report to the BIOS the current interrupt model used by the OS"¹.
That method is called _PIC. So calling _PIC(1) tells the BIOS the OS has
chosen to run in APIC mode and gives the BIOS the possibility to make
adjustments. Now that is where the BIOS should _disable_ all sources of
As the implementation of how to disable boot interrupts is really
chipset specific it's the BIOSes task to disable them in the APIC mode
case. All the boot interrupt quirks we've been adding to the kernel are
just workarounds for buggy BIOSes!
An example of how this can look like, taken from the AMD SB700/710/750
BIOS developers guide²:
During the BIOS POST, the BIOS will do normal PCI IRQ routing through
port C00h/C01h. Once APIC is fully enabled by the OS, the routing in
C00h/C01 must be all cleared to zero. The following is a sample ASL code
that may be incorporated into the BIOS:
Method(_PIC, 0x01, NotSerialized)
Store (Arg0, PICF)
\_SB.PCI0.LPC0.DSPI() // clear interrupt at 0xC00/0xC01
[...] (full implementation snipped)
Note: 0xC00/0xC01 are the PCI interrupt mapping registers in this case.
It's not that hard to do once you're aware of it.
This is a call to all chipset manufacturers/BIOS developers/everyone
involved: Please get the appropriate changes into your BIOS/BIOS
developers guide! Thanks!
¹ ACPI Specification 4.0 (sec 5.8.1)
² http://developer.amd.com/assets/43366_sb7xx_bdg_pub_1.00.pdf (sec 10.5)
Stefan Assmann | Red Hat GmbH
Software Engineer | Otto-Hahn-Strasse 20, 85609 Dornach
| HR: Amtsgericht Muenchen HRB 153243
| GF: Brendan Lane, Charlie Peters,
sassmann at redhat.com | Michael Cunningham, Charles Cachera
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