[coreboot] [Fwd: Re: arima hdama problem]

[Hugh Greenberg]

I tried it from power on again and I got the same thing.  Below is the 
output after I applied your patch and did a hard reset:

coreboot-2.3 Fri Oct 16 15:29:39 MDT 2009 starting...
Enabling routing table for node 00 done.
Enabling SMP settings
(0,1) link=01
(1,0) link=01
setup_remote_node: done
Renaming current temporary node to 01 done.
Enabling routing table for node 01 done.
02 nodes initialized.
coherent_ht_finalize
done
SBLink=00
NC node|link=00
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x35
pos=0xce, unfiltered freq_cap=0x35
freq_cap1=0x35, freq_cap2=0x15
dev1 old_freq=0x4, freq=0x4, needs_reset=0x0
dev2 old_freq=0x4, freq=0x4, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
entering ht_optimize_link
pos=0xd2, unfiltered freq_cap=0x35
pos=0xce, unfiltered freq_cap=0x1
pos=0xce, filtered freq_cap=0x1
freq_cap1=0x15, freq_cap2=0x1
dev1 old_freq=0x0, freq=0x0, needs_reset=0x0
dev2 old_freq=0x0, freq=0x0, needs_reset=0x0
width_cap1=0x0, width_cap2=0x0
dev1 input ln_width1=0x3, ln_width2=0x3
dev1 input width=0x0
dev1 output ln_width1=0x3, ln_width2=0x3
dev1 input|output width=0x0
old dev1 input|output width=0x0
dev2 input|output width=0x0
old dev2 input|output width=0x0
SMBus controller enabled
Ram1.00
setting up CPU00 northbridge registers
done.
Ram1.01
setting up CPU01 northbridge registers
done.
Ram2.00
Enabling dual channel memory
Registered
166Mhz
RAM end at 0x00100000 kB
Lower RAM end at 0x00100000 kB
Ram2.01
Enabling dual channel memory
Registered
166Mhz
RAM end at 0x00200000 kB
Lower RAM end at 0x00200000 kB
Ram3
print_k8regs: func 0 (c0000)
0x40 (Routing 0) 50101
0x44 (Routing 1) 10404
0x60 (Node ID) 10010
print_k8regs: func 1 (c1000)
0x40 (DRAM Base) 3
0x44 (DRAM Lim) 3f0000
0x48 (DRAM Base) 400003
0x4C (DRAM Lim) 7f0001
b8 fc0003
bc ffff00
c0 3
c4 1fff000
e0 3f000003
print_k8regs: func 2 (c2000) nonzero only
40 (DRAM Base) 1
60 (DRAM Base) 3e0fe00
80 (DRAM Base) 4
while waiting for BSP signal to STOP, timeout in ap 01

-- 
Hugh Greenberg
Los Alamos National Laboratory, CCS-1
Email: hng at lanl.gov
Phone: (505) 665-6471



Myles Watson wrote:
>
>
> On Fri, Oct 16, 2009 at 2:28 PM, Hugh Greenberg <hng at lanl.gov 
> <mailto:hng at lanl.gov>> wrote:
>
>     I'm getting more output now with r4795:
>
> Good.  Thanks.
>  
>
>     coreboot-2.3 Fri Oct 16 14:19:51 MDT 2009 starting...
>     Enabling routing table for node 00 done.
>     Enabling SMP settings
>      
>
>     (0,1) link=01
>     (1,0) link=01
>     setup_remote_node: done
>     Renaming current temporary node to 01 done.
>     Enabling routing table for node 01 done.
>     02 nodes initialized.
>     coherent_ht_finalize
>     done
>
>     SBLink=00
>     NC node|link=00
>     entering ht_optimize_link
>     pos=0x8a, unfiltered freq_cap=0x8075
>     pos=0x8a, filtered freq_cap=0x35
>     pos=0xce, unfiltered freq_cap=0x35
>     freq_cap1=0x35, freq_cap2=0x15
>     dev1 old_freq=0x4, freq=0x4, needs_reset=0x0
>     dev2 old_freq=0x4, freq=0x4, needs_reset=0x0
>
> This looks like a warm reset.  Have you tried it from power on?
>  
> I have no idea why it would stop there.  The next thing I would do is 
> print out the routing table when it hangs.
>
> Thanks,
> Myles