[coreboot] [v2] r4736 - in trunk/coreboot-v2/src: mainboard/dell/s1850 superio/nsc/pc8374
svn at coreboot.org
svn at coreboot.org
Wed Oct 7 20:03:41 CEST 2009
Author: rminnich
Date: 2009-10-07 20:03:41 +0200 (Wed, 07 Oct 2009)
New Revision: 4736
Added:
trunk/coreboot-v2/src/superio/nsc/pc8374/pc8374_early_init.c
Removed:
trunk/coreboot-v2/src/superio/nsc/pc8374/pc8374_early_serial.c
Modified:
trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c
Log:
Get rid of early_serial, it is now a generic function in early_init.
Add some more enables to the s1850.
Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Stefan Reinauer <stepan at coresystems.de>
Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c 2009-10-07 16:29:12 UTC (rev 4735)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c 2009-10-07 18:03:41 UTC (rev 4736)
@@ -13,7 +13,7 @@
#include "lib/ramtest.c"
#include "southbridge/intel/i82801er/i82801er_early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
-#include "superio/nsc/pc8374/pc8374_early_serial.c"
+#include "superio/nsc/pc8374/pc8374_early_init.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "debug.c"
@@ -65,6 +65,25 @@
}
static inline int spd_read_byte(unsigned device, unsigned address)
{
+ /* fake it out for this board */
+ switch(device) {
+ case 0x52:
+ case 0x53:
+ print_debug("FAKE");
+ device = 0x50;
+ break;
+ case 0x50:
+ case 0x51:
+ case 0x54:
+ case 0x55:
+ case 0x56:
+ case 0x57:
+ print_debug("57");
+ device = 0x57;
+ break;
+ default:
+ die("BAD DEV IN spd_read_byte");
+ }
return smbus_read_byte(device, address);
}
@@ -191,11 +210,22 @@
.f1 = PCI_DEV(0, 0x00, 1),
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
- .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
- .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
+ .channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, },
+ .channel1 = {(0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, (0xa<<3)|7, },
}
};
+ /* superio setup */
+ /* observed from serialice */
+ static const u8 earlyinit[] = {
+ 0x21, 0x11, 0x11,
+ 0x22, 1, 1,
+ 0x23, 05, 05,
+ 0x24, 0x81, 0x81,
+ 0x26, 0, 0,
+ 0,
+ };
+
/* using SerialICE, we've seen this basic reset sequence on the dell.
* we don't understand it as it uses undocumented registers, but
* we're going to clone it.
@@ -261,10 +291,10 @@
pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
/* ?? */
- l = pci_read_config32(PCI_DEV(0, 0, 8), 0xc0);
+ l = pci_read_config32(PCI_DEV(0, 8, 0), 0xc0);
do_reset = l & 0x8000000;
l |= 0x8000000;
- pci_write_config32(PCI_DEV(0, 0, 2), 0xc0, l);
+ pci_write_config32(PCI_DEV(0, 8, 0), 0xc0, l);
if (! do_reset) {
outb(2, 0xcf9);
@@ -279,11 +309,26 @@
}
/* Setup the console */
mainboard_set_ich5();
- bmc_foad();
- pc8374_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
+ //bmc_foad();
+ pc8374_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
+ /* stuff we seem to need */
+ pc8374_enable_dev(PC8374_KBCK, 0);
+
+ /* GPIOs */
+ pc8374_enable_dev(PC8374_GPIO, 0xc20);
+
+ /* keep this in mind.
+ SerialICE-hlp: outb 002e <= 23
+ SerialICE-hlp: inb 002f => 05
+ SerialICE-hlp: outb 002f <= 05
+ SerialICE-hlp: outb 002e <= 24
+ SerialICE-hlp: inb 002f => c1
+ SerialICE-hlp: outb 002f <= c1
+ */
+
/* Halt if there was a built in self test failure */
// report_bist_failure(bist);
@@ -306,7 +351,7 @@
#if 1
enable_smbus();
#endif
-#if 1
+#if 0
// dump_spd_registers(&cpu[0]);
int i;
for(i = 0; i < 1; i++) {
Added: trunk/coreboot-v2/src/superio/nsc/pc8374/pc8374_early_init.c
===================================================================
--- trunk/coreboot-v2/src/superio/nsc/pc8374/pc8374_early_init.c (rev 0)
+++ trunk/coreboot-v2/src/superio/nsc/pc8374/pc8374_early_init.c 2009-10-07 18:03:41 UTC (rev 4736)
@@ -0,0 +1,37 @@
+#include <arch/romcc_io.h>
+#include "pc8374.h"
+
+/* things that Must Be Done to get this chip working */
+/* Straight from the data book */
+static void pc8374_enable(unsigned iobase, u8 *init)
+{
+ u8 val, count;
+ outb(0x29, iobase);
+ val = inb(iobase+1);
+ val |= 0x91;
+ outb(val, iobase+1);
+ for(count = 0; count < 255; count++)
+ if (inb(iobase+1) == 0x91)
+ break;
+ for(;*init; init++) {
+ outb(*init, iobase);
+ val = inb(iobase+1);
+ init++;
+ val &= *init;
+ init++;
+ val |= *init;
+ outb(val, iobase+1);
+ }
+
+
+}
+
+static void pc8374_enable_dev(device_t dev, unsigned iobase)
+{
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ if (iobase)
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+}
+
Property changes on: trunk/coreboot-v2/src/superio/nsc/pc8374/pc8374_early_init.c
___________________________________________________________________
Added: svn:mergeinfo
+
Deleted: trunk/coreboot-v2/src/superio/nsc/pc8374/pc8374_early_serial.c
===================================================================
--- trunk/coreboot-v2/src/superio/nsc/pc8374/pc8374_early_serial.c 2009-10-07 16:29:12 UTC (rev 4735)
+++ trunk/coreboot-v2/src/superio/nsc/pc8374/pc8374_early_serial.c 2009-10-07 18:03:41 UTC (rev 4736)
@@ -1,11 +0,0 @@
-#include <arch/romcc_io.h>
-#include "pc8374.h"
-
-
-static void pc8374_enable_serial(device_t dev, unsigned iobase)
-{
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 1);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
-}
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