[coreboot] failing fam10 code in coreboot

Myles Watson mylesgw at gmail.com
Thu Nov 19 15:29:13 CET 2009



> Myles,
> 
> The newest release of coreboot doesnt build at all for fam10 code
> anymore. 
Sorry about that.  The latest should be fixed now.  Sending that report to
the list could have saved you some time.

> Therefore, I am sorry it took so long to get back to you.
> Making the stack bigger did the trick, thanks a bunch! The drawback
> however is that it fails at the end of the bootprocess now once coreboot
> tries to load the payload (filo 0.5).
I think that's unrelated, but maybe Patrick can help.

> To answer the remainder of your questions:
> I mostly use the ubuntu gcc 4.3.3 toolchain. I also tried building
> 3.4.6 toolchain based code which generally produces faster executables
> and often fails at a wholly different point in the booting process.
It makes sense if there's memory corruption that it would be different based
on the tool chain.

> Afaik, with fam10 code, it is only possible to use the buildtarget
> approach
> as fam10 code doesnt fit into the limited failover space and therefore
> will
> not yet work with the cbfs scheme (16bit jump
> operation issue if reportings on the mailing list are right).
Hopefully that will be fixed very soon.  Only 50 more revs till 5000.

Thanks,
Myles

High Tables Base is dfff0000.                   
i=0 bus range: [0, 4] bus_isa=5                 
Writing IRQ routing tables to 0xf0000...done.   
Writing IRQ routing tables to 0xdfff0000...done.
Wrote the mp table end at: 000f0410 - 000f06a4  
Wrote the mp table end at: dfff0410 - dfff06a4  
Moving GDT to 0xdfff0800...ok                   
Multiboot Information structure has been written.
Writing high table forward entry at 0x00000500   
Wrote coreboot table at: 00000500 - 00000518  checksum 13df
New low_table_end: 0x00000518                              
Now going to write high coreboot table at 0xdfff0c00       
rom_table_end = 0xdfff0c00                                 
Adjust low_table_end from 0x00000518 to 0x00001000         
Adjust rom_table_end from 0xdfff0c00 to 0xe0000000         
Adding high table area                                     
Wrote coreboot table at: dfff0c00 - dfff1514  checksum 82a6
Check fallback/payload                                     
Got a payload                                              
Loading segment from rom address 0xfff00038                
  parameter section (skipped)                              
Loading segment from rom address 0xfff00054                
  data (compression=0)                                     
  New segment dstaddr 0x100000 memsize 0x39d630 srcaddr 0xfff000d8 filesize
0x15f20
  (cleaned up) New segment addr 0x100000 size 0x39d630 offset 0xfff000d8
filesize 0x15f20
Loading segment from rom address 0xfff00070

  data (compression=0)

  New segment dstaddr 0x49d630 memsize 0x48 srcaddr 0xfff15ff8 filesize 0x48

  (cleaned up) New segment addr 0x49d630 size 0x48 offset 0xfff15ff8
filesize 0x48       
Loading segment from rom address 0xfff0008c

  Entry Point 0x00100080

Loading Segment: addr: 0x0000000000100000 memsz: 0x000000000039d630 filesz:
0x0000000000015f20
Post relocation: addr: 0x00000000dfc529d0 memsz: 0x0000000000100000 filesz:
0x0000000000000000
Loading Segment: addr: 0x0000000000300000 memsz: 0x000000000019d630 filesz:
0x0000000000000000
Post relocation: addr: 0x0000000000300000 memsz: 0x000000000019d630 filesz:
0x0000000000000000
Loading Segment: addr: 0x000000000049d630 memsz: 0x0000000000000048 filesz:
0x0000000000000048
Post relocation: addr: 0x000000000049d630 memsz: 0x0000000000000048 filesz:
0x0000000000000048
it's not compressed!

dest 49d630, end 49d678, bouncebuffer dfc529d0

Jumping to boot code at 100080




INIT detected from  --- {        APICID = 00 NODEID = 00 COREID = 00} ---

Issuing SOFT_RESET...





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