[coreboot] Uh oh, looks like trouble...

Joshua McDowell jmcdowell at issisolutions.com
Wed May 20 21:47:33 CEST 2009

Hash: SHA1

Interestingly enough, I was able to get linux bios from the chip, just
not correctly.  The starting address wasn't correct and I don't think I
got the whole thing.  I doubt intel will help, and I will alert you the
second I have access to the storage that I think has the source code.


ron minnich wrote:
> On Wed, May 20, 2009 at 11:37 AM, Joshua McDowell
> <jmcdowell at issisolutions.com> wrote:
>>  Maybe they can help, maybe not.
> oh, the vendor *can* help. But will they help? In the past they have
> made it clear that it is not their policy to release this kind of
> info. You don't need info on the flash part; you need info on the
> mainboard itself.
> The kind of info is found in the linux kernel in drivers/mtd/maps, in
> files like this:
> alchemy-flash.c     ipaq-flash.c        rbtx4939-flash.c
> amd76xrom.c         ixp2000.c           redwood.c
> autcpu12-nvram.c    ixp4xx.c            rpxlite.c
> bfin-async-flash.c  Kconfig             sa1100-flash.c
> cdb89712.c          l440gx.c            sbc8240.c
> ceiva.c             Makefile            sbc_gxx.c
> cfi_flagadm.c       map_funcs.c         sc520cdp.c
> ck804xrom.c         mbx860.c            scb2_flash.c
> dbox2-flash.c       netsc520.c          scx200_docflash.c
> dc21285.c           nettel.c            solutionengine.c
> dilnetpc.c          octagon-5066.c      sun_uflash.c
> dmv182.c            omap_nor.c          tqm8xxl.c
> edb7312.c           pci.c               ts5500_flash.c
> esb2rom.c           pcmciamtd.c         tsunami_flash.c
> fortunet.c          physmap.c           uclinux.c
> h720x-flash.c       physmap_of.c        vmax301.c
> ichxrom.c           plat-ram.c          vmu-flash.c
> impa7.c             pmcmsp-flash.c      wr_sbc82xx_flash.c
> integrator-flash.c  pmcmsp-ramroot.c
> intel_vr_nor.c      pxa2xx-flash.c
> Let's look at one of interest, for example, the l440gx.c. In it you
> find code like this:
> 	/* Set the iobase */
> 	iobase = pm_iobase->start;
> 	pci_write_config_dword(pm_dev, 0x40, iobase | 1);
> 	/* Set XBCS# */
> 	pci_read_config_word(dev, 0x4e, &word);
> 	word |= 0x4;
>         pci_write_config_word(dev, 0x4e, word);
> 	/* Supply write voltage to the chip */
> 	l440gx_set_vpp(&l440gx_map, 1);
> 	/* Enable the gate on the WE line */
> 	outb(inb(TRIBUF_PORT) & ~1, TRIBUF_PORT);
>        	printk(KERN_NOTICE "Enabled WE line to L440GX BIOS flash chip.\n");
> The key line follows the comment: /* Enable the gate on the WE line */
> This is the kind of code that enables mainboard flash writes. A lot of
> the board support in mtd is old; vendors don't help much with this
> kind of information, as they are scared of the dreaded BIOS virus.
> But this is what we need. I was hoping MTD had it; I don't know how
> LBFLASH fixed the WE problem, but if you can get us source we can try
> to see.
> ron

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