[coreboot] Failed flash, flashrom emergency help needed on ICH7

[Peter Stuge]

Ali Nadalizadeh wrote:
> I'm also online on #coreboot as nadalizadeh

Some analysis after Ali worked with Carl-Daniel and me to debug this.

The chip needs a write enable command to set it's write enable latch
before each erase or write command.

flashrom sends this as a separate command, but for software sequenced
ICH SPI that doesn't work, it needs to go into the ICH PREOP register
and not be sent as an individual command.

Because this fails when trying to send an erase command, chip erase
aborts. Ignoring that write enable error allows the erase to
continue, and succeed.

This chip doesn't support writes of more than one byte at a time
using the 02 command, but the flashrom ICH SPI driver (and maybe
others) assumes that all chips support more data in one go. Many do.

Ali had to go, and we have to rest a little, right now the machine is
running AAI programming, writing two bytes at a time.

If that doesn't work either, the next step is to try the 02 byte
program command but actually send only a single byte at a time.
(force maxdata=1 somewhere suitable)

More updates this afternoon. I think it'll work in the end.


//Peter