[coreboot] Custom VGA Driver - Help
Joseph Smith
joe at settoplinux.org
Mon Mar 23 13:32:18 CET 2009
Hello,
I am trying to setup a custom vga driver to run code before and after the
vga rom executes. It builds and runs ok but I can't seem to get any of my
output to show (yes my debug level is set 9). Do vga option roms not use
the device ops (pci_dev_init())? Am I doing something wrong(patch and
bootlog attached)?
--
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
-------------- next part --------------
Index: src/northbridge/intel/i82830/Config.lb
===================================================================
--- src/northbridge/intel/i82830/Config.lb (revision 4025)
+++ src/northbridge/intel/i82830/Config.lb (working copy)
@@ -20,3 +20,4 @@
config chip.h
object northbridge.o
+object vga.o
Index: src/northbridge/intel/i82830/vga.c
===================================================================
--- src/northbridge/intel/i82830/vga.c (revision 0)
+++ src/northbridge/intel/i82830/vga.c (revision 0)
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Joseph Smith <joe at settoplinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+
+static void vga_init(device_t dev) {
+
+ printk_debug("Start test - Before pci_dev_init\n");
+
+ pci_dev_init(dev);
+
+ printk_debug("End test - After pci_dev_init\n");
+}
+
+static const struct device_operations vga_operations = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = vga_init,
+ .scan_bus = 0,
+ .enable = 0,
+ .ops_pci = 0,
+};
+
+static const struct pci_driver vga_driver __pci_driver = {
+ .ops = &vga_operations,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = 0x3577,
+};
-------------- next part --------------
coreboot-2.0.0_RM4100 Sun Mar 22 23:35:19 EDT 2009 starting...
SMBus controller enabled
Found DIMM in slot 01
DIMM is 0x0080 on side 1
DIMM is 0x0000 on side 2
Found DIMM in slot 01, setting DRA...
Uncompressing coreboot to RAM.
Jumping to coreboot.
coreboot-2.0.0_RM4100 Sun Mar 22 23:35:19 EDT 2009 booting...
Calibrating delay loop...
end 641f08fb, start 7a8a7cd
32-bit delta 1479
calibrate_tsc 32-bit result is 1479
clocks_per_usec: 1479
Enumerating buses...
scan_static_bus for Root Device
Finding PCI configuration type.
PCI: Using configuration type 1
PCI_DOMAIN: 0000 enabled
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/3575] ops
PCI: 00:00.0 [8086/3575] enabled
PCI: 00:01.0, bad id 0xffffffff
PCI: 00:02.0 [8086/3577] enabled
PCI: 00:03.0, bad id 0xffffffff
PCI: 00:04.0, bad id 0xffffffff
PCI: 00:05.0, bad id 0xffffffff
PCI: 00:06.0, bad id 0xffffffff
PCI: 00:07.0, bad id 0xffffffff
PCI: 00:08.0, bad id 0xffffffff
PCI: 00:09.0, bad id 0xffffffff
PCI: 00:0a.0, bad id 0xffffffff
PCI: 00:0b.0, bad id 0xffffffff
PCI: 00:0c.0, bad id 0xffffffff
PCI: 00:0d.0, bad id 0xffffffff
PCI: 00:0e.0, bad id 0xffffffff
PCI: 00:0f.0, bad id 0xffffffff
PCI: 00:10.0, bad id 0xffffffff
PCI: 00:11.0, bad id 0xffffffff
PCI: 00:12.0, bad id 0xffffffff
PCI: 00:13.0, bad id 0xffffffff
PCI: 00:14.0, bad id 0xffffffff
PCI: 00:15.0, bad id 0xffffffff
PCI: 00:16.0, bad id 0xffffffff
PCI: 00:17.0, bad id 0xffffffff
PCI: 00:18.0, bad id 0xffffffff
PCI: 00:19.0, bad id 0xffffffff
PCI: 00:1a.0, bad id 0xffffffff
PCI: 00:1b.0, bad id 0xffffffff
PCI: 00:1c.0, bad id 0xffffffff
PCI: 00:1d.0 [8086/24c2] ops
PCI: 00:1d.0 [8086/24c2] enabled
PCI: 00:1d.1 [8086/24c4] ops
PCI: 00:1d.1 [8086/24c4] enabled
PCI: 00:1d.2 [8086/24c7] ops
PCI: 00:1d.2 [8086/24c7] enabled
PCI: 00:1d.3, bad id 0xffffffff
PCI: 00:1d.4, bad id 0xffffffff
PCI: 00:1d.5, bad id 0xffffffff
PCI: 00:1d.6, bad id 0xffffffff
PCI: 00:1d.7 [8086/24cd] ops
PCI: 00:1d.7 [8086/24cd] enabled
PCI: 00:1e.0 [8086/244e] bus ops
PCI: 00:1e.0 [8086/244e] enabled
PCI: 00:1f.0 [8086/24c0] bus ops
PCI: 00:1f.0 [8086/24c0] enabled
PCI: 00:1f.1 [8086/24cb] ops
PCI: 00:1f.1 [8086/24cb] enabled
PCI: 00:1f.2, bad id 0xffffffff
PCI: 00:1f.3 [8086/24c3] enabled
PCI: 00:1f.4, bad id 0xffffffff
PCI: 00:1f.5 [8086/24c5] ops
PCI: 00:1f.5 [8086/24c5] enabled
PCI: 00:1f.6 [8086/24c6] ops
PCI: 00:1f.6 [8086/24c6] enabled
PCI: 00:1f.7, bad id 0xffffffff
do_pci_scan_bridge for PCI: 00:1e.0
PCI: pci_scan_bus for bus 01
PCI: 01:00.0, bad id 0xffffffff
PCI: 01:01.0, bad id 0xffffffff
PCI: 01:02.0, bad id 0xffffffff
PCI: 01:03.0, bad id 0xffffffff
PCI: 01:04.0, bad id 0xffffffff
PCI: 01:05.0, bad id 0xffffffff
PCI: 01:06.0, bad id 0xffffffff
PCI: 01:07.0, bad id 0xffffffff
PCI: 01:08.0 [8086/103a] ops
PCI: 01:08.0 [8086/103a] enabled
PCI: 01:09.0, bad id 0xffffffff
PCI: 01:0a.0, bad id 0xffffffff
PCI: 01:0b.0, bad id 0xffffffff
PCI: 01:0c.0, bad id 0xffffffff
PCI: 01:0d.0, bad id 0xffffffff
PCI: 01:0e.0, bad id 0xffffffff
PCI: 01:0f.0, bad id 0xffffffff
PCI: 01:10.0, bad id 0xffffffff
PCI: 01:11.0, bad id 0xffffffff
PCI: 01:12.0, bad id 0xffffffff
PCI: 01:13.0, bad id 0xffffffff
PCI: 01:14.0, bad id 0xffffffff
PCI: 01:15.0, bad id 0xffffffff
PCI: 01:16.0, bad id 0xffffffff
PCI: 01:17.0, bad id 0xffffffff
PCI: 01:18.0, bad id 0xffffffff
PCI: 01:19.0, bad id 0xffffffff
PCI: 01:1a.0, bad id 0xffffffff
PCI: 01:1b.0, bad id 0xffffffff
PCI: 01:1c.0, bad id 0xffffffff
PCI: 01:1d.0, bad id 0xffffffff
PCI: 01:1e.0, bad id 0xffffffff
PCI: 01:1f.0, bad id 0xffffffff
PCI: pci_scan_bus returning with max=001
do_pci_scan_bridge returns max 1
scan_static_bus for PCI: 00:1f.0
Found SMSC Super I/O (ID=0x60, rev=0x01)
PNP: 002e.0 disabled
PNP: 002e.3 enabled
PNP: 002e.4 enabled
PNP: 002e.5 enabled
PNP: 002e.7 enabled
PNP: 002e.9 disabled
PNP: 002e.a enabled
PNP: 002e.b disabled
scan_static_bus for PCI: 00:1f.0 done
PCI: pci_scan_bus returning with max=001
scan_static_bus for Root Device done
done
Allocating resources...
Reading resources...
Root Device compute_allocate_resource io: base: 00000400 size: 00000000 align: 0 gran: 0
Root Device read_resources bus 0 link: 0
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
PCI: 00:00.0 register 10(00000008), read-only ignoring it
PCI: 00:1e.0 compute_allocate_resource io: base: 00000000 size: 00000000 align: 12 gran: 12
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 01:08.0 14 * [0x00000000 - 0x0000003f] io
PCI: 00:1e.0 compute_allocate_resource io: base: 00000040 size: 00001000 align: 12 gran: 12 done
PCI: 00:1e.0 compute_allocate_resource prefmem: base: 00000000 size: 00000000 align: 20 gran: 20
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 00:1e.0 compute_allocate_resource prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 done
PCI: 00:1e.0 compute_allocate_resource prefmem: base: fff00000 size: 00000000 align: 20 gran: 20
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 00:1e.0 compute_allocate_resource prefmem: base: fff00000 size: 00000000 align: 20 gran: 20 done
PCI: 00:1e.0 24 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:1e.0 compute_allocate_resource mem: base: 00000000 size: 00000000 align: 20 gran: 20
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 01:08.0 10 * [0x00000000 - 0x00000fff] mem
PCI: 00:1e.0 compute_allocate_resource mem: base: 00001000 size: 00100000 align: 20 gran: 20 done
PCI: 00:1f.0 read_resources bus 0 link: 0
PCI: 00:1f.0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
PCI: 00:1e.0 1c * [0x00001000 - 0x00001fff] io
PCI: 00:1f.5 10 * [0x00002000 - 0x000020ff] io
PCI: 00:1f.6 10 * [0x00002400 - 0x000024ff] io
PCI: 00:1f.6 14 * [0x00002800 - 0x0000287f] io
PCI: 00:1f.5 14 * [0x00002880 - 0x000028bf] io
PCI: 00:1d.0 20 * [0x000028c0 - 0x000028df] io
PCI: 00:1d.1 20 * [0x000028e0 - 0x000028ff] io
PCI: 00:1d.2 20 * [0x00002c00 - 0x00002c1f] io
PCI: 00:1f.3 20 * [0x00002c20 - 0x00002c3f] io
PCI: 00:1f.1 20 * [0x00002c40 - 0x00002c4f] io
PCI: 00:1f.1 10 * [0x00002c50 - 0x00002c57] io
PCI: 00:1f.1 18 * [0x00002c60 - 0x00002c67] io
PCI: 00:1f.1 14 * [0x00002c70 - 0x00002c73] io
PCI: 00:1f.1 1c * [0x00002c80 - 0x00002c83] io
Root Device compute_allocate_resource io: base: 00002c84 size: 00002884 align: 12 gran: 0 done
Root Device compute_allocate_resource mem: base: 00000000 size: 00000000 align: 0 gran: 0
Root Device read_resources bus 0 link: 0
Root Device read_resources bus 0 link: 0 done
PCI: 00:02.0 10 * [0x00000000 - 0x07ffffff] prefmem
PCI: 00:1e.0 20 * [0x08000000 - 0x080fffff] mem
PCI: 00:02.0 14 * [0x08100000 - 0x0817ffff] mem
PCI: 00:1d.7 10 * [0x08180000 - 0x081803ff] mem
PCI: 00:1f.1 24 * [0x08181000 - 0x081813ff] mem
PCI: 00:1f.5 18 * [0x08182000 - 0x081821ff] mem
PCI: 00:1f.5 1c * [0x08183000 - 0x081830ff] mem
Root Device compute_allocate_resource mem: base: 08183100 size: 08183100 align: 27 gran: 0 done
Done reading resources.
Allocating VGA resource PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Setting resources...
Root Device compute_allocate_resource io: base: 00001000 size: 00002884 align: 12 gran: 0
Root Device read_resources bus 0 link: 0
Root Device read_resources bus 0 link: 0 done
PCI: 00:1e.0 1c * [0x00001000 - 0x00001fff] io
PCI: 00:1f.5 10 * [0x00002000 - 0x000020ff] io
PCI: 00:1f.6 10 * [0x00002400 - 0x000024ff] io
PCI: 00:1f.6 14 * [0x00002800 - 0x0000287f] io
PCI: 00:1f.5 14 * [0x00002880 - 0x000028bf] io
PCI: 00:1d.0 20 * [0x000028c0 - 0x000028df] io
PCI: 00:1d.1 20 * [0x000028e0 - 0x000028ff] io
PCI: 00:1d.2 20 * [0x00002c00 - 0x00002c1f] io
PCI: 00:1f.3 20 * [0x00002c20 - 0x00002c3f] io
PCI: 00:1f.1 20 * [0x00002c40 - 0x00002c4f] io
PCI: 00:1f.1 10 * [0x00002c50 - 0x00002c57] io
PCI: 00:1f.1 18 * [0x00002c60 - 0x00002c67] io
PCI: 00:1f.1 14 * [0x00002c70 - 0x00002c73] io
PCI: 00:1f.1 1c * [0x00002c80 - 0x00002c83] io
Root Device compute_allocate_resource io: base: 00002c84 size: 00001c84 align: 12 gran: 0 done
Root Device compute_allocate_resource mem: base: f0000000 size: 08183100 align: 27 gran: 0
Root Device read_resources bus 0 link: 0
Root Device read_resources bus 0 link: 0 done
PCI: 00:02.0 10 * [0xf0000000 - 0xf7ffffff] prefmem
PCI: 00:1e.0 20 * [0xf8000000 - 0xf80fffff] mem
PCI: 00:02.0 14 * [0xf8100000 - 0xf817ffff] mem
PCI: 00:1d.7 10 * [0xf8180000 - 0xf81803ff] mem
PCI: 00:1f.1 24 * [0xf8181000 - 0xf81813ff] mem
PCI: 00:1f.5 18 * [0xf8182000 - 0xf81821ff] mem
PCI: 00:1f.5 1c * [0xf8183000 - 0xf81830ff] mem
Root Device compute_allocate_resource mem: base: f8183100 size: 08183100 align: 27 gran: 0 done
Root Device assign_resources, bus 0 link: 0
Setting RAM size to 122880
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:02.0 10 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x1b prefmem
PCI: 00:02.0 14 <- [0x00f8100000 - 0x00f817ffff] size 0x00080000 gran 0x13 mem
PCI: 00:02.0 30 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x00 romem
PCI: 00:1d.0 20 <- [0x00000028c0 - 0x00000028df] size 0x00000020 gran 0x05 io
PCI: 00:1d.1 20 <- [0x00000028e0 - 0x00000028ff] size 0x00000020 gran 0x05 io
PCI: 00:1d.2 20 <- [0x0000002c00 - 0x0000002c1f] size 0x00000020 gran 0x05 io
PCI: 00:1d.7 10 <- [0x00f8180000 - 0x00f81803ff] size 0x00000400 gran 0x0a mem
PCI: 00:1e.0 compute_allocate_resource io: base: 00001000 size: 00001000 align: 12 gran: 12
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 01:08.0 14 * [0x00001000 - 0x0000103f] io
PCI: 00:1e.0 compute_allocate_resource io: base: 00001040 size: 00001000 align: 12 gran: 12 done
PCI: 00:1e.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io
PCI: 00:1e.0 compute_allocate_resource mem: base: f8000000 size: 00100000 align: 20 gran: 20
PCI: 00:1e.0 read_resources bus 1 link: 0
PCI: 00:1e.0 read_resources bus 1 link: 0 done
PCI: 01:08.0 10 * [0xf8000000 - 0xf8000fff] mem
PCI: 00:1e.0 compute_allocate_resource mem: base: f8001000 size: 00100000 align: 20 gran: 20 done
PCI: 00:1e.0 20 <- [0x00f8000000 - 0x00f80fffff] size 0x00100000 gran 0x14 bus 01 mem
PCI: 00:1e.0 assign_resources, bus 1 link: 0
PCI: 01:08.0 10 <- [0x00f8000000 - 0x00f8000fff] size 0x00001000 gran 0x0c mem
PCI: 01:08.0 14 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
PCI: 00:1e.0 assign_resources, bus 1 link: 0
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PNP: 002e.3 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io
PNP: 002e.3 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq
PNP: 002e.3 74 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 drq
PNP: 002e.4 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 002e.4 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 002e.5 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
PNP: 002e.5 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
PNP: 002e.7 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
PNP: 002e.7 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
PNP: 002e.7 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
PNP: 002e.7 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
PNP: 002e.a 60 <- [0x0000000800 - 0x00000007ff] size 0x00000000 gran 0x00 io
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PCI: 00:1f.1 10 <- [0x0000002c50 - 0x0000002c57] size 0x00000008 gran 0x03 io
PCI: 00:1f.1 14 <- [0x0000002c70 - 0x0000002c73] size 0x00000004 gran 0x02 io
PCI: 00:1f.1 18 <- [0x0000002c60 - 0x0000002c67] size 0x00000008 gran 0x03 io
PCI: 00:1f.1 1c <- [0x0000002c80 - 0x0000002c83] size 0x00000004 gran 0x02 io
PCI: 00:1f.1 20 <- [0x0000002c40 - 0x0000002c4f] size 0x00000010 gran 0x04 io
PCI: 00:1f.1 24 <- [0x00f8181000 - 0x00f81813ff] size 0x00000400 gran 0x0a mem
PCI: 00:1f.3 20 <- [0x0000002c20 - 0x0000002c3f] size 0x00000020 gran 0x05 io
PCI: 00:1f.5 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
PCI: 00:1f.5 14 <- [0x0000002880 - 0x00000028bf] size 0x00000040 gran 0x06 io
PCI: 00:1f.5 18 <- [0x00f8182000 - 0x00f81821ff] size 0x00000200 gran 0x09 mem
PCI: 00:1f.5 1c <- [0x00f8183000 - 0x00f81830ff] size 0x00000100 gran 0x08 mem
PCI: 00:1f.6 10 <- [0x0000002400 - 0x00000024ff] size 0x00000100 gran 0x08 io
PCI: 00:1f.6 14 <- [0x0000002800 - 0x000000287f] size 0x00000080 gran 0x07 io
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Done allocating resources.
Enabling resources...
PCI: 00:00.0 cmd <- 06
PCI: 00:02.0 subsystem <- 00/00
PCI: 00:02.0 cmd <- 03
PCI: 00:1d.0 cmd <- 01
PCI: 00:1d.1 cmd <- 01
PCI: 00:1d.2 cmd <- 01
PCI: 00:1d.7 subsystem <- 00/00
PCI: 00:1d.7 cmd <- 02
PCI: 00:1e.0 bridge ctrl <- 0003
PCI: 00:1e.0 cmd <- 07
PCI: 01:08.0 cmd <- 03
PCI: 00:1f.0 cmd <- 0f
PCI: 00:1f.1 cmd <- 03
PCI: 00:1f.3 subsystem <- 00/00
PCI: 00:1f.3 cmd <- 01
PCI: 00:1f.5 cmd <- 03
PCI: 00:1f.6 cmd <- 01
done.
Initializing devices...
Root Device init
PCI: 00:00.0 init
Northbridge init
PCI: 00:02.0 init
rom address for PCI: 00:02.0 = fff00000
PCI Expansion ROM, signature 0xaa55, INIT size 0x10000, data ptr 0x0040
PCI ROM Image, Vendor 8086, Device 3577,
PCI ROM Image, Class Code 030000, Code Type 00
copying VGA ROM Image from fff00000 to 0xc0000, 0x10000 bytes
PCI: 00:1d.0 init
PCI: 00:1d.1 init
PCI: 00:1d.2 init
PCI: 00:1d.7 init
EHCI: Setting up controller.. done.
PCI: 00:1e.0 init
PCI: 00:1f.0 init
IOAPIC Southbridge enabled 2186
Southbridge APIC ID = 2000000
Set power on if power fails
RTC Init
PNP: 002e.3 init
PNP: 002e.4 init
PNP: 002e.5 init
PNP: 002e.7 init
Keyboard init...
PNP: 002e.a init
PCI: 00:1f.1 init
IDE0 IDE1 PCI: 00:1f.3 init
APIC_CLUSTER: 0 init
malloc Enter, size 1100, free_mem_ptr 0003a000
malloc 0003a000
Initializing CPU #0
CPU: vendor Intel device 6b4
CPU: family 06, model 0b, stepping 04
Enabling cache
Setting fixed MTRRs(0-88) Type: UC
Setting fixed MTRRs(0-16) Type: WB
DONE fixed MTRRs
call enable_fixed_mtrr()
Setting variable MTRR 0, base: 0MB, range: 64MB, type WB
ADDRESS_MASK_HIGH=0xf
Setting variable MTRR 1, base: 64MB, range: 32MB, type WB
ADDRESS_MASK_HIGH=0xf
Setting variable MTRR 2, base: 96MB, range: 16MB, type WB
ADDRESS_MASK_HIGH=0xf
Setting variable MTRR 3, base: 112MB, range: 8MB, type WB
ADDRESS_MASK_HIGH=0xf
Zero-sized MTRR range @0KB
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
microcode_info: sig = 0x000006b4 pf=0x00000020 rev = 0x00000000
Disabling local apic...done.
CPU #0 initialized
Devices initialized
Copying Interrupt Routing Table to 0x000f0000... done.
Moving GDT to 0x500...ok
Multiboot Information structure has been written.
Adjust low_table_end from 0x00000530 to 0x00001000
Adjust rom_table_end from 0x000f04b8 to 0x00100000
Wrote coreboot table at: 00000530 - 0000073c checksum c16
elfboot: Attempting to load payload.
rom_stream: 0xfff10000 - 0xfffdffff
Found ELF candidate at offset 0
header_offset is 0
Try to load at offset 0x0
malloc Enter, size 32, free_mem_ptr 0003a44c
malloc 0003a44c
New segment addr 0x100000 size 0x39c8b0 offset 0xe0 filesize 0x15160
(cleaned up) New segment addr 0x100000 size 0x39c8b0 offset 0xe0 filesize 0x15160
lb: [0x0000000000004000, 0x000000000003e000)
malloc Enter, size 32, free_mem_ptr 0003a46c
malloc 0003a46c
New segment addr 0x49c8b0 size 0x48 offset 0x15240 filesize 0x48
(cleaned up) New segment addr 0x49c8b0 size 0x48 offset 0x15240 filesize 0x48
lb: [0x0000000000004000, 0x000000000003e000)
Dropping non PT_LOAD segment
Dropping non PT_LOAD segment
Dropping non PT_LOAD segment
Loading Segment: addr: 0x0000000000100000 memsz: 0x000000000039c8b0 filesz: 0x0000000000015160
[ 0x0000000000100000, 0000000000115160, 0x000000000049c8b0) <- 00000000000000e0
Clearing Segment: addr: 0x0000000000115160 memsz: 0x0000000000387750
Loading Segment: addr: 0x000000000049c8b0 memsz: 0x0000000000000048 filesz: 0x0000000000000048
[ 0x000000000049c8b0, 000000000049c8f8, 0x000000000049c8f8) <- 0000000000015240
Loaded segments
verified segments
closed down stream
Jumping to boot code at 0010007c
entry = 0x0010007c
lb_start = 0x00004000
lb_size = 0x0003a000
adjust = 0x077c2000
buffer = 0x0778c000
elf_boot_notes = 0x000242e0
adjusted_boot_notes = 0x077e62e0
FILO version 0.6.0rc1 (joe at smitty6) Sun Mar 8 22:23:41 EDT 2009
No USB stack in libpayload.
ERROR: No such CMOS option (boot_devices)
Press <Enter> for default menu.lst (hdc1:/grub/grub.conf), or <Esc> for prompt... 5 4 3 2 1 timed out
menu: hdc1:/grub/grub.conf
IDE time outreset failed, but we may be on SATADrive 2 does not existDrive 2 does not existCould not open menu.lst file 'hdc1:/grub/grub.conf'. Entering command line. FILO 0.6.0rc1 [ Minimal BASH-like line editing is supported. For the first word, TAB lists possible command completions.] FILO 0.6.0rc1 [ Minimal BASH-like line editing is supported. For the first word, TAB lists possible command completions.] filo>
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