[coreboot] r1157 - coreboot-v3/northbridge/amd/geodelx

[Peter Stuge]

Peter Stuge wrote:
> I suggest that this patch does not change how the code works.

This time with attachment.

//Peter
-------------- next part --------------
Index: raminit.c
===================================================================
--- raminit.c	(revision 1157)
+++ raminit.c	(working copy)
@@ -345,40 +345,42 @@
 
 	/* DIMM 0 */
 	casmap0 = spd_read_byte(dimm0, SPD_ACCEPTABLE_CAS_LATENCIES);
-	if (casmap0 != 0xFF) {
-		/* If -.5 timing is supported, check -.5 timing > GeodeLink. */
-		/* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5 */
-		spd_byte = spd_read_byte(dimm0, SPD_SDRAM_CYCLE_TIME_2ND);
-		if (spd_byte != 0) {
-			/* Turn SPD ns time into MHz. Check what the asm does
-			 * to this math.
-			 */
-			dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
-			if (dimm_speed >= glspeed) {
-				/* If -1 timing is supported, check -1 timing > GeodeLink. */
-				/* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1 */
-				spd_byte = spd_read_byte(dimm0, SPD_SDRAM_CYCLE_TIME_3RD);
-				if (spd_byte != 0) {
-					/* Turn SPD ns time into MHz. Check what the asm does to this math. */
-					dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
-					if (dimm_speed <= glspeed) {
-						/* Set we can use -.5 timing but not -1. */
-						spd_byte = 31 - __builtin_clz((u32) casmap0);
-						/* Just want bits in the lower byte since we have to cast to a 32. */
-						casmap0 &= 0xFF << (--spd_byte);
-					}
-				}	/* MIN_CYCLE_10 != 0 */
-			} else {
-				/* Timing_05 < GLspeed, can't use -.5 or -1 timing. */
-				spd_byte = 31 - __builtin_clz((u32) casmap0);
-				/* Just want bits in the lower byte since we have to cast to a 32. */
-				casmap0 &= 0xFF << (spd_byte);
-			}
-		}		/* MIN_CYCLE_05 != 0 */
-	} else {		/* No DIMM */
+	if (0xff == casmap0) {	/* No DIMM */
 		casmap0 = 0;
+		goto dimm1;
 	}
 
+	/* If -.5 timing is supported, check -.5 timing > GeodeLink. */
+	/* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5 */
+	spd_byte = spd_read_byte(dimm0, SPD_SDRAM_CYCLE_TIME_2ND);
+	if (0 == spd_byte)
+		goto dimm1;
+
+	/* Turn SPD ns time into MHz. Check what the asm does to this math. */
+	dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
+	if (dimm_speed >= glspeed) {
+		/* If -1 timing is supported, check -1 timing > GeodeLink. */
+		/* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1 */
+		spd_byte = spd_read_byte(dimm0, SPD_SDRAM_CYCLE_TIME_3RD);
+		if (0 == spd_byte)
+			goto dimm1;
+
+		/* Turn SPD ns time into MHz. Check what the asm does to this math. */
+		dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
+		if (dimm_speed > glspeed)
+			goto dimm1;
+
+		--spd_byte;
+		/* MIN_CYCLE_10 != 0 */
+	}
+
+	/* Set we can use -.5 timing but not -1. */
+	spd_byte = 31 - __builtin_clz((u32) casmap0);
+	/* Just want bits in the lower byte since we have to cast to a 32. */
+	casmap0 &= 0xFF << (spd_byte);
+	/* MIN_CYCLE_05 != 0 */
+
+dimm1:
 	/* DIMM 1 */
 	casmap1 = spd_read_byte(dimm1, SPD_ACCEPTABLE_CAS_LATENCIES);
 	if (casmap1 != 0xFF) {